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Datasheet Actel A1020B-2PQ100C

Производитель:Actel
Семейство:ACT 1
Серия:A1020B
Модель:A1020B-2PQ100C

Серия FPGA ACT 1

Datasheets

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    IC FPGA 2K GATES 100-PQFP COM
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Варианты написания: A1020B2PQ100C, A1020B 2PQ100C

Выписка из документа:
ACTTM 1 Series FPGAs
Features 5V and 3.3V Families fully compatible with JEDEC specifications Up to 2000 Gate Array Gates (6000 PLD equivalent gates) Replaces up to 50 TTL Packages Replaces up to twenty 20-Pin PAL® Packages Design Library with over 250 Macro Functions Gate Array Architecture Allows Completely Automatic Place and Route Up to 547 Programmable Logic Modules Up to 273 Flip-Flops Data Rates to 75 MHz Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 25 MHz Built-In High Speed Clock Distribution Network I/O Drive to 10 mA (5 V), 6 mA (3.3 V) Nonvolatile, User Programmable Fabricated in 1.0 micron CMOS technology
Description A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered.
Product Family Profile
Device Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages 20-Pin PAL Equivalent Packages Logic Modules Flip-Flops (maximum) Routing Resources Horizontal Tracks/Channel Vertical Tracks/Column PLICE Antifuse Elements User I/Os (maximum) Packages: A1010B A10V10B 1,200 3,000 30 12 295 147 22 13 112,000 57 44 PLCC 68 PLCC A1020B A10V20B 2,000 6,000 50 20 547 273 22 13 186,000 69 The ACTTM 1 Series of field programmable gate arrays (FPGAs) offers a variety of package, speed, and application combinations. Devices are implemented in silicon gate, 1-micron two-level metal CMOS, and they employ Actel's PLICE® antifuse technology. The unique architecture offers gate array flexibility, high performance, and instant turnaround through user programming. Device utilization is typically 95 to 100 percent of available logic modules. ACT 1 devices also provide system designers with unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. Additional features include an on-chip clock driver with a hardwired distribution network. The network provides efficient clock distribution with minimum skew. The us...

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