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Производитель:Texas Instruments

Схема очистки от джиттера сигнала синхронизации.


На английском языке: Datasheet Texas Instruments LMK04821NKDT

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community LMK04821, LMK04826, LMK04828
SNAS605AQ ­ MARCH 2013 ­ REVISED AUGUST 2014 LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
1 Features 1 2 Applications Wireless Infrastructure Data Converter Clocking Networking, SONET/SDH, DSLAM Medical / Video / Military / Aerospace Test and Measurement JEDEC JESD204B Support Ultra-Low RMS Jitter ­ 88 fs RMS jitter (12 kHz to 20 MHz) ­ 91 fs RMS jitter (100 Hz to 20 MHz) ­ ­162.5 dBc/Hz Noise Floor at 245.76 MHz Up to 14 Differential Device Clocks from PLL2 ­ Up to 7 SYSREF Clocks ­ Maximum Clock Output Frequency 3.1 GHz ­ LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2 Up to 1 Buffered VCXO/Crystal Output from PLL1 ­ LVPECL, LVDS, 2xLVCMOS Programmable Dual Loop PLLatinumTM PLL Architecture PLL1 ­ Up to 3 Redundant Input Clocks ­ Automatic and Manual Switch-over Modes ­ Hitless Switching and LOS ­ Integrated Low-Noise Crystal Oscillator Circuit ­ Holdover mode when Input Clocks are lost PLL2 ­ Normalized [1 Hz] PLL Noise Floor of -227 dBc/Hz ­ Phase Detector Rate up to 155 MHz ­ OSCin Frequency-doubler ­ Two Integrated Low-Noise VCOs 50% Duty Cycle Output Divides, 1 to 32 (even and odd) Precision Digital Delay, Dynamically Adjustable 25 ps Step Analog Delay Multi-mode: Dual PLL, single PLL, and Clock Distribution Industrial Temperature Range: -40 to 85°C 3.15 V to 3.45 ...

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