Datasheet Texas Instruments THS1031CPW — Даташит
| Производитель | Texas Instruments |
| Серия | THS1031 |
| Модель | THS1031CPW |
10-битный аналого-цифровой преобразователь (АЦП) с быстродействием 30 MSPS 28-TSSOP от 0 до 70
Datasheets
3-V to 5.5-V, 10-Bit, 30 MSPS CMOS Analog-to-Digital Converter datasheet
PDF, 728 Кб, Версия: E, Файл опубликован: 21 мар 2002
Выписка из документа
Цены
 Купить THS1031CPW на РадиоЛоцман.Цены — от 344 до 55 686 ₽14 предложений от 11 поставщиков 10-Bit, 30-MSPS Analog-to-Digital Converter (ADC) 28-TSSOP 0 to 70 | |||
| THS1031CPW Texas Instruments | от 344 ₽ | ||
| THS1031CPW Texas Instruments | 453 ₽ | ||
| THS1031CPW Texas Instruments | 508 ₽ | ||
| THS1031CPW Texas Instruments | по запросу | ||
Статус
| Статус продукта | В производстве (Рекомендуется для новых разработок) |
| Доступность образцов у производителя | Нет |
Корпус / Упаковка / Маркировка
| Pin | 28 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 50 |
| Carrier | TUBE |
| Маркировка | TH1031 |
| Width (мм) | 4.4 |
| Length (мм) | 9.7 |
| Thickness (мм) | 1 |
| Pitch (мм) | .65 |
| Max Height (мм) | 1.2 |
| Mechanical Data | Скачать |
Параметры
| # Input Channels | 1 |
| Analog Input BW | 150 МГц |
| Архитектура | Pipeline |
| DNL(Max) | 1 +/-LSB |
| DNL(Typ) | 0.3 +/-LSB |
| ENOB | 8.8 Bits |
| INL(Max) | 2 +/-LSB |
| INL(Typ) | 1 +/-LSB |
| Input Buffer | No |
| Input Range | 2 Vp-p |
| Interface | Parallel CMOS |
| Рабочий диапазон температур | от 0 до 70 C |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP) PKG |
| Power Consumption(Typ) | 160 mW |
| Rating | Catalog |
| Reference Mode | Ext,Int |
| Разрешение | 10 Bits |
| SFDR | 52.4 дБ |
| SINAD | 56 дБ |
| SNR | 49.3 дБ |
| Sample Rate(Max) | 30 MSPS |
Экологический статус
| RoHS | Совместим |
Комплекты разработчика и оценочные наборы
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Статус продукта: В производстве (Рекомендуется для новых разработок)
Application Notes
- Using TI FIFOs to Interface High-Speed Data Converters With TI TMS320 DSPsPDF, 249 Кб, Файл опубликован: 8 июн 2001
Most high-speed data converters cannot be connected directly to a digital signal processor (DSP). The required transfer rates would tie up most of the DSP's I/O bandwidth. A FIFO is an appropriate solution for this problem because it can buffer a large block of data, and the DSP can read data from the FIFO in a burst mode. This is much more efficient compared to single reads for every sampled valu - CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Кб, Файл опубликован: 4 сен 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Кб, Файл опубликован: 28 апр 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Кб, Версия: A, Файл опубликован: 10 сен 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Мб, Файл опубликован: 2 июн 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Кб, Файл опубликован: 8 июн 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Noise Analysis for High Speed Op Amps (Rev. A)PDF, 256 Кб, Версия: A, Файл опубликован: 17 янв 2005
As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu
Модельный ряд
Серия: THS1031 (7)
Классификация производителя
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)
