Datasheet Texas Instruments OMAP3530 — Даташит

Производитель	Texas Instruments
Серия	OMAP3530

Datasheets

Цены

Купить OMAP3530 на РадиоЛоцман.Цены — от 5.54 до 9 954 ₽ 27 предложений от 20 поставщиков OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
AiPCBA Весь мир	OMAP3530ECBBLPD Texas Instruments	5.54 ₽	Купить
ChipWorker Весь мир	OMAP3530ECBBLPD Texas Instruments	5.66 ₽	Купить
EIS Components Весь мир	OMAP3530DCBB72 Texas Instruments	71 ₽	Купить
ЭлектроПласт Россия	OMAP3530-HiRel Texas Instruments	по запросу	Купить

Статус

Корпус / Упаковка / Маркировка

Параметры

Parameters / Models	3530ECBCAMERCURY	3530ECUSAGRM	OMAP3530DCBB	OMAP3530DCBB72	OMAP3530DCBBA	OMAP3530DCBC	OMAP3530DCBC72	OMAP3530DCBCA	OMAP3530DCUS	OMAP3530DCUS72	OMAP3530DCUSA	OMAP3530ECBB	OMAP3530ECBB72	OMAP3530ECBBA	OMAP3530ECBBALPD	OMAP3530ECBBAR	OMAP3530ECBBLPD	OMAP3530ECBC	OMAP3530ECBC72	OMAP3530ECBCA	OMAP3530ECUS	OMAP3530ECUS72	OMAP3530ECUSA
2D & 3D Graphics			Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated	Hardware Accelerated
ARM CPU			1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8
ARM MHz, Max.												720	720	720	720	720	720	720	720	720	720	720	720
ARM MHz (Max.)			720	720	720	720	720	720	720	720	720
Approx. Price (US$)			52.08 | 100u	52.08 | 100u	52.08 | 100u	52.08 | 100u	52.08 | 100u	52.08 | 100u	52.08 | 100u	52.08 | 100u	52.08 | 100u
Approx. price, US$	40.212 | 100u	40.212 | 100u
Arm CPU	1 Arm Cortex-A8	1 Arm Cortex-A8
Arm MHz, Max.	720	720
CPU	32-bit	32-bit
Co-processor, s	GPU,DSP	GPU,DSP
Display type	Parallel Digital Output,Up to 24-Bit RGB Compatible,HD Maximum Resolution ?? ETM Interface,Supports Up to 2 LCD Panels,Support for Remote Frame Buffer,Interface (RFBI) LCD Panels	Parallel Digital Output,Up to 24-Bit RGB Compatible,HD Maximum Resolution ?? ETM Interface,Supports Up to 2 LCD Panels,Support for Remote Frame Buffer,Interface (RFBI) LCD Panels
Integrated TI C64x DSP			Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz	Up to 520 MHz
Memory Interface, Dual Channel												1 16-bit LPDDR , 1 32-bit SDRC	1 16-bit LPDDR , 1 32-bit SDRC	1 16-bit LPDDR , 1 32-bit SDRC	1 16-bit LPDDR , 1 32-bit SDRC	1 16-bit LPDDR , 1 32-bit SDRC	1 16-bit LPDDR , 1 32-bit SDRC	1 16-bit LPDDR , 1 32-bit SDRC	1 16-bit LPDDR , 1 32-bit SDRC	1 16-bit LPDDR , 1 32-bit SDRC	1 16-bit LPDDR , 1 32-bit SDRC	1 16-bit LPDDR , 1 32-bit SDRC	1 16-bit LPDDR , 1 32-bit SDRC
Memory Interface (Dual Channel)			1 16-bit LPDDR 1 32-bit SDRC	1 16-bit LPDDR 1 32-bit SDRC	1 16-bit LPDDR 1 32-bit SDRC	1 16-bit LPDDR 1 32-bit SDRC	1 16-bit LPDDR 1 32-bit SDRC	1 16-bit LPDDR 1 32-bit SDRC	1 16-bit LPDDR 1 32-bit SDRC	1 16-bit LPDDR 1 32-bit SDRC	1 16-bit LPDDR 1 32-bit SDRC
Operating system	Linux,RTOS	Linux,RTOS
Operating temperature range, C	-40 to 105,0 to 90	-40 to 105,0 to 90
Package Group	FCBGA|423,POP-FCBGA|515	FCBGA|423,POP-FCBGA|515
Package size: mm2:W x L, PKG	423FCBGA: 256 mm2: 16 x 16 (FCBGA|423),515POP-FCBGA: 144 mm2: 12 x 12 (POP-FCBGA|515)	423FCBGA: 256 mm2: 16 x 16 (FCBGA|423),515POP-FCBGA: 144 mm2: 12 x 12 (POP-FCBGA|515)
Performance			D1	D1	D1	D1	D1	D1	D1	D1	D1	D1	D1	D1	D1	D1	D1	D1	D1	D1	D1	D1	D1
Process Node			65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm	65nm
Rating	Catalog	Catalog

Экологический статус

Application Notes

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  OMAP3530 Power Consumption Summary
  PDF, 19 Кб, Файл опубликован: 8 янв 2010
  This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute visit this topic at: http://wiki.davincidsp.com/index.php/OMAP3530_Power_Estimation_Spreadsheet.

  Power consumption on the OMAP3530 device is highly application-dependent therefore a sp

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  OMAP3530 Easy CUS Package PCB Escape Routing (Rev. A)
  PDF, 2.6 Мб, Версия: A, Файл опубликован: 25 мар 2010
  The OMAP3530 CUS package is designed with a new technology called Via Channel™ array. This technology allows for easy routing of the device in two signal and two power layers using standard 20 mil diameter and 10 mil finished hole size via; it is cost and time effective. This application report shows how to easily route the entire package by first routing one quadrant only and then copying i
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  Ultrasound Scan Conversion on TI's C64x+ DSPs
  PDF, 656 Кб, Файл опубликован: 3 апр 2009
  One of the recent significant developments in ultrasound is the emergence of portable and handheld ultrasound machines and their rapid acceptance in the market place.Because of their power efficiency and high performance digital signal processor (DSP) based devices have been increasingly used as the main processing engine in these portable and hand carried units.

  This application report dis

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  OMAP35x Linux PSP Data Sheet
  PDF, 1.6 Мб, Файл опубликован: 16 окт 2009
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  OMAP3530/25/15/03 CBB CBC & CUS Reflow Profiles
  PDF, 27 Кб, Файл опубликован: 13 ноя 2009
  This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute visit this topic at:

  http://wiki.davincidsp.com/index.php/OMAP3_CBB_CBC_CUS_Reflow_Profiles

  Reflow profiles are dependent on numerous factors including package type number of components bo

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  OMAP35x 0.65mm Pitch Layout Methods (Rev. B)
  PDF, 372 Кб, Версия: B, Файл опубликован: 26 июн 2008
  It is easy to see from the unique look that the OMAP35x parts have a very unusual footprint. The OMAP35x ball grid array is designed with new technology called the Via Channel array which makes significant printed circuit board (PCB) cost savings possible. If the PCB is routed correctly this cost savings can be substantial. This application report explains how this is possible and shows several
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  Powering OMAP3 With TPS65023: Design-In Guide (Rev. B)
  PDF, 181 Кб, Версия: B, Файл опубликован: 2 мар 2009
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  OMAP35x to AM35x Hardware Migration Guide
  PDF, 19 Кб, Файл опубликован: 24 май 2010
  This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute visit this topic at:

  http://processors.wiki.ti.com/index.php/OMAP35x_to_AM35x_Hardware_Migration_Guide.

  This article describes hardware device considerations to migrate a design

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  OMAP35x to AM37x Hardware Migration Guide
  PDF, 37 Кб, Файл опубликован: 3 июн 2010
  This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute visit this topic at:

  http://processors.wiki.ti.com/index.php/OMAP35x_To_AM37x_Hardware_Migration_Guide.

  The OMAP35x to AM37x Hardware Migration Guide describes device consideratio

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  PCB Design Guidelines for 0.4mm Package-On-Package (PoP) Packages Part I (Rev. B)
  PDF, 6.7 Мб, Версия: B, Файл опубликован: 13 июн 2009
  Ball grid array (BGA) packages having 0.4mm ball pitch require careful attention to printed circuit board (PCB) design parameters to successfully yield reliable and robust assemblies; the standard rules of thumb don't apply anymore. In fact the design guidelines for 0.4mm and 0.5mm differ primarily due to issues surrounding shorts or opens between balls under the processor.In addition to the de
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  PCB Assembly Guidelines for 0.4mm Package-On-Package (PoP) Packages Part II (Rev. A)
  PDF, 2.4 Мб, Версия: A, Файл опубликован: 1 ноя 2013
  Once the bottom circuit board has been designed the assembly guidelines for package-on-package (PoP) versions of the OMAP35xx processor and the memory device must be considered.

  PoP packages have an enormous number of variables associated with assembly. The following factors have a major effect on the quality and reliability of final assembly: the circuit board design the solder paste char

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  PCB Assembly Guidelines for 0.5mm Package-on-Package Apps Processors Part II
  PDF, 1.2 Мб, Файл опубликован: 23 июн 2010
  Once the main printed circuit board (PCB) has been designed the assembly guidelines for the 0.5mm package-on-package (PoP) applications processor and companion memory device must be considered. PoP applications processors have an enormous number of variables associated with assembly. The following factors have a major effect on the quality and reliability of PCB assembly: PoP applications process
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  PCB Design Guidelines for 0.5mm Package-On-Package Apps Processors Part I
  PDF, 2.0 Мб, Файл опубликован: 23 июн 2010
  Ball grid array (BGA) packages having 0.5mm ball pitch require careful attention to printed circuit board (PCB) design parameters to successfully yield reliable and robust assemblies. PCBs with package-on-package (PoP) technology have additional assembly requirements and options that need to be considered when designing the PCB.

  Fine-pitch PCB design is a team effort and may require more than

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  Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms
  PDF, 969 Кб, Файл опубликован: 24 сен 2009
  This application report describes the device differences to be taken care for running the C64x+™ video codec software on different C64x+ based platforms. This document assumes that the codec software is developed for the C64x+ digital signal processor (DSP) core. As many TI platforms have a C64x+ DSP this document gives the details for running the standalone codec software on a C64x+ platfo
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  Introduction to TMS320C6000 DSP Optimization
  PDF, 535 Кб, Файл опубликован: 6 окт 2011
  The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then

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