Datasheet Texas Instruments SN74ALVC16821 — Даташит
| Производитель | Texas Instruments |
| Серия | SN74ALVC16821 |
3.3-V 20-Bit Bus-Interface Flip-Flop with 3-State Outputs
Datasheets
3.3-V 20-Bit Bus-Interface Flip-Flop With 3-State Outputs (Rev. A)
PDF, 186 Кб, Версия: A, Файл опубликован: 1 авг 1995
Цены
| SN74ALVC16821DLR Texas Instruments | по запросу | ||
Статус
| SN74ALVC16821DL | SN74ALVC16821DLR | |
|---|---|---|
| Статус продукта | Снят с производства | Снят с производства |
| Доступность образцов у производителя | Нет | Нет |
Корпус / Упаковка / Маркировка
| SN74ALVC16821DL | SN74ALVC16821DLR | |
|---|---|---|
| N | 1 | 2 |
| Pin | 56 | 56 |
| Package Type | DL | DL |
| Industry STD Term | SSOP | SSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Width (мм) | 7.49 | 7.49 |
| Length (мм) | 18.41 | 18.41 |
| Thickness (мм) | 2.59 | 2.59 |
| Pitch (мм) | .635 | .635 |
| Max Height (мм) | 2.79 | 2.79 |
| Mechanical Data | Скачать | Скачать |
Экологический статус
| SN74ALVC16821DL | SN74ALVC16821DLR | |
|---|---|---|
| RoHS | Не совместим | Не совместим |
| Бессвинцовая технология (Pb Free) | Нет | Нет |
Application Notes
- TI SN74ALVC16835 Component Specification Analysis for PC100PDF, 43 Кб, Файл опубликован: 3 авг 1998
The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T - Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)PDF, 96 Кб, Версия: A, Файл опубликован: 13 май 1998
Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large - 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)PDF, 895 Кб, Версия: B, Файл опубликован: 22 май 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa - Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)PDF, 154 Кб, Версия: A, Файл опубликован: 8 сен 1999
In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families
Модельный ряд
Серия: SN74ALVC16821 (2)
Классификация производителя
- Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop
