Datasheet Texas Instruments SN74ALVCH374 — Даташит
| Производитель | Texas Instruments |
| Серия | SN74ALVCH374 |
Octal Positive-Edge-Triggered D-Type Flip-Flop With 3-State Outputs
Datasheets
SN74ALVCH374 datasheet
PDF, 834 Кб, Версия: G, Файл опубликован: 3 сен 2004
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Цены
 Купить SN74ALVCH374 на РадиоЛоцман.Цены — от 21 до 83 ₽23 предложений от 19 поставщиков Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295, 7.50mm Width) | |||
| SN74ALVCH374DGVR Texas Instruments | 21 ₽ | ||
| SN74ALVCH374N Texas Instruments | 26 ₽ | ||
| SN74ALVCH374N Texas Instruments | от 61 ₽ | ||
| SN74ALVCH374PWRE4 Texas Instruments | по запросу | ||
Статус
| SN74ALVCH374DGVR | SN74ALVCH374DW | SN74ALVCH374PW | SN74ALVCH374PWR | |
|---|---|---|---|---|
| Статус продукта | В производстве | В производстве | В производстве | В производстве |
| Доступность образцов у производителя | Да | Нет | Нет | Нет |
Корпус / Упаковка / Маркировка
| SN74ALVCH374DGVR | SN74ALVCH374DW | SN74ALVCH374PW | SN74ALVCH374PWR | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 20 | 20 | 20 | 20 |
| Package Type | DGV | DW | PW | PW |
| Industry STD Term | TVSOP | SOIC | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 2000 | 25 | 70 | 2000 |
| Carrier | LARGE T&R | TUBE | TUBE | LARGE T&R |
| Маркировка | VB374 | ALVCH374 | VB374 | VB374 |
| Width (мм) | 4.4 | 7.5 | 4.4 | 4.4 |
| Length (мм) | 5 | 12.8 | 6.5 | 6.5 |
| Thickness (мм) | 1.05 | 2.35 | 1 | 1 |
| Pitch (мм) | .4 | 1.27 | .65 | .65 |
| Max Height (мм) | 1.2 | 2.65 | 1.2 | 1.2 |
| Mechanical Data | Скачать | Скачать | Скачать | Скачать |
Параметры
| Parameters / Models | SN74ALVCH374DGVR | SN74ALVCH374DW | SN74ALVCH374PW | SN74ALVCH374PWR |
|---|---|---|---|---|
| 3-State Output | Yes | Yes | Yes | Yes |
| Bits | 8 | 8 | 8 | 8 |
| F @ Nom Voltage(Max), Mhz | 150 | 150 | 150 | 150 |
| ICC @ Nom Voltage(Max), мА | 0.01 | 0.01 | 0.01 | 0.01 |
| Рабочий диапазон температур, C | от -40 до 85 | от -40 до 85 | от -40 до 85 | от -40 до 85 |
| Output Drive (IOL/IOH)(Max), мА | 24/-24 | 24/-24 | 24/-24 | 24/-24 |
| Package Group | TVSOP | SOIC | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 20TVSOP: 32 mm2: 6.4 x 5(TVSOP) | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) |
| Rating | Catalog | Catalog | Catalog | Catalog |
| Schmitt Trigger | No | No | No | No |
| Technology Family | ALVC | ALVC | ALVC | ALVC |
| VCC(Max), В | 3.6 | 3.6 | 3.6 | 3.6 |
| VCC(Min), В | 1.65 | 1.65 | 1.65 | 1.65 |
| Voltage(Nom), В | 1.8,2.5,2.7,3.3 | 1.8,2.5,2.7,3.3 | 1.8,2.5,2.7,3.3 | 1.8,2.5,2.7,3.3 |
| tpd @ Nom Voltage(Max), нс | 6.4,3.9,3.6 | 6.4,3.9,3.6 | 6.4,3.9,3.6 | 6.4,3.9,3.6 |
Экологический статус
| SN74ALVCH374DGVR | SN74ALVCH374DW | SN74ALVCH374PW | SN74ALVCH374PWR | |
|---|---|---|---|---|
| RoHS | Совместим | Совместим | Совместим | Совместим |
Application Notes
- TI SN74ALVC16835 Component Specification Analysis for PC100PDF, 43 Кб, Файл опубликован: 3 авг 1998
The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T - Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)PDF, 96 Кб, Версия: A, Файл опубликован: 13 май 1998
Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large - Bus-Hold CircuitPDF, 418 Кб, Файл опубликован: 5 фев 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of - 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)PDF, 895 Кб, Версия: B, Файл опубликован: 22 май 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa - Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)PDF, 154 Кб, Версия: A, Файл опубликован: 8 сен 1999
In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families
Модельный ряд
Серия: SN74ALVCH374 (4)
Классификация производителя
- Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop
