Datasheet Texas Instruments ADS808Y/250 — Даташит
| Производитель | Texas Instruments |
| Серия | ADS808 |
| Модель | ADS808Y/250 |
12-битный аналого-цифровой преобразователь (АЦП) с быстродействием 70 MSPS 48-HTQFP от -40 до 85
Datasheets
ADS808: 12-Bit, 70MHz Sampling Analog-to-Digital Converter datasheet
PDF, 1.0 Мб, Версия: C, Файл опубликован: 4 сен 2002
Выписка из документа
Цены
 Купить ADS808Y/250 на РадиоЛоцман.Цены — от 2 193 до 319 287 ₽10 предложений от 10 поставщиков 12Bit, 70MSPS ADC SE/Diff, Int/Ext ef., Flexible Clocking, Selectable Fullscale ange & Powerdown 48-HTQFP -40℃ to 85℃ | |||
| ADS808Y/250G4 Texas Instruments | 2 193 ₽ | ||
| ADS808Y/250G4 Texas Instruments | 3 183 ₽ | ||
| ADS808Y/250G4 Texas Instruments | 3 558 ₽ | ||
| ADS808Y250 | 319 287 ₽ | ||
Статус
| Статус продукта | В производстве (Рекомендуется для новых разработок) |
| Доступность образцов у производителя | Нет |
Корпус / Упаковка / Маркировка
| Pin | 48 |
| Package Type | PHP |
| Industry STD Term | HTQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 250 |
| Carrier | SMALL T&R |
| Маркировка | ADS808Y |
| Width (мм) | 7 |
| Length (мм) | 7 |
| Thickness (мм) | 1 |
| Pitch (мм) | .5 |
| Max Height (мм) | 1.2 |
| Mechanical Data | Скачать |
Параметры
| # Input Channels | 1 |
| Analog Input BW | 1000 МГц |
| Архитектура | Pipeline |
| DNL(Max) | 1.7 +/-LSB |
| DNL(Typ) | 0.7 +/-LSB |
| ENOB | 10.3 Bits |
| INL(Max) | 7 +/-LSB |
| INL(Typ) | 4 +/-LSB |
| Input Buffer | No |
| Input Range | 1,2 Vp-p |
| Interface | Parallel CMOS |
| Рабочий диапазон температур | от -40 до 85 C |
| Package Group | HTQFP |
| Package Size: mm2:W x L | 48HTQFP: 81 mm2: 9 x 9(HTQFP) PKG |
| Power Consumption(Typ) | 720 mW |
| Rating | Catalog |
| Reference Mode | Ext,Int |
| Разрешение | 12 Bits |
| SFDR | 68 дБ |
| SINAD | 64 дБ |
| SNR | 64 дБ |
| Sample Rate(Max) | 70 MSPS |
Экологический статус
| RoHS | Совместим |
Комплекты разработчика и оценочные наборы
- Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Статус продукта: В производстве (Рекомендуется для новых разработок)
Application Notes
- Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Кб, Версия: A, Файл опубликован: 18 май 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Кб, Версия: B, Файл опубликован: 9 окт 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Кб, Версия: A, Файл опубликован: 10 сен 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Кб, Файл опубликован: 8 июн 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Мб, Файл опубликован: 2 июн 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Кб, Версия: A, Файл опубликован: 16 апр 2015
- CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Кб, Файл опубликован: 4 сен 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Кб, Файл опубликован: 28 апр 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
Модельный ряд
Серия: ADS808 (1)
- ADS808Y/250
Классификация производителя
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)
