AD743ABSOLUTE MAXIMUM RATINGS1ORDERING GUIDE Supply Voltage . ± 18 V Internal Power Dissipation2 TemperaturePackage Input Voltage . ± V ModelRangeOption* S Output Short Circuit Duration . Indefinite AD743JN 0°C to 70°C N-8 Differential Input Voltage . +VS and –VS AD743JR-16 0°C to 70°C R-16 Storage Temperature Range (N, R) . –65°C to +125°C AD743JR-16-REEL 0°C to 70°C Tape and Reel Operating Temperature Range AD743JR-16-REEL7 0°C to 70°C Tape and Reel AD743J . 0°C to 70°C *N = PDIP; R = SOIC. Lead Temperature Range (Soldering 60 sec) . 300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-lead PDIP: JA = 100°C/W, JC = 30°C/W. 16-lead SOIC: JA = 100°C/W, JC = 30°C/W. ESD SUSCEPTIBILITY An ESD classification per method 3015.6 of MIL-STD-883C has been performed on the AD743. The AD743 is a Class 1 device, passing at 1000 V and failing at 1500 V on null Pins 1 and 5, when tested, using an IMCS 5000 automated ESD tester. Pins other than null pins fail at greater than 2500 V. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD743 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. E –3– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS CONNECTION DIAGRAMS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD SUSCEPTIBILITY ORDERING GUIDE Typical Performance Characteristics OP AMP PERFORMANCE: JFET VS. BIPOLAR DESIGNING CIRCUITS FOR LOW NOISE LOW NOISE CHARGE AMPLIFIERS HOW CHIP PACKAGE TYPE AND POWER DISSIPATION AFFECT INPUT BIAS CURRENT REDUCED POWER SUPPLY OPERATION FOR LOWER IB AN INPUT IMPEDANCE COMPENSATED, SALLEN-KEY FILTER TWO HIGH PERFORMANCE ACCELEROMETER AMPLIFIERS LOW NOISE HYDROPHONE AMPLIFIER BALANCING SOURCE IMPEDANCES OUTLINE DIMENSIONS Revision History
