LTC2241-10 10-Bit, 210Msps ADC FEATURESDESCRIPTION n Sample Rate: 210Msps The LTC®2241-10 is a 210Msps, sampling 10-bit A/D con- n 60.5dB SNR verter designed for digitizing high frequency, wide dynamic n 78dB SFDR range signals. The LTC2241-10 is perfect for demanding n 1.2GHz Full Power Bandwidth S/H communications applications with AC performance that n Single 2.5V Supply includes 60.5dB SNR and 78dB SFDR. Ultralow jitter of n Low Power Dissipation: 585mW 95fsRMS allows IF undersampling with excellent noise n LVDS, CMOS, or Demultiplexed CMOS Outputs performance. n Selectable Input Ranges: ±0.5V or ±1V DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ) n No Missing Codes and no missing codes over temperature. n Optional Clock Duty Cycle Stabilizer n Shutdown and Nap Modes The digital outputs can be either differential LVDS, or n Data Ready Output Clock single-ended CMOS. There are three format options for n Pin Compatible Family the CMOS outputs: a single bus running at the full data 250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit) rate or two demultiplexed buses running at half data rate 210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit) with either interleaved or simultaneous update. A separate 170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit) output power supply allows the CMOS output swing to 185Msps: LTC2220-1 (12-Bit)* range from 0.5V to 2.625V. 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)* The ENC+ and ENC– inputs may be driven differentially or 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)* single ended with a sine wave, PECL, LVDS, TTL, or CMOS n 64-Pin 9mm × 9mm QFN Package inputs. An optional clock duty cycle stabilizer allows high APPLICATIONS performance over a wide range of clock duty cycles. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. n Wireless and Wired Broadband Communication All other trademarks are the property of their respective owners. *LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts. n Cable Head-End Systems n Power Amplifi er Linearization n Communications Test Equipment TYPICAL APPLICATION 2.5V VDD SFDR vs Input Frequency 0.5V REFH 85 FLEXIBLE TO 2.625V REFL REFERENCE 80 OVDD 75 + D9 70 10-BIT • CMOS ANALOG INPUT CORRECTION OUTPUT PIPELINED • OR INPUT S/H LOGIC DRIVERS 65 ADC CORE • LVDS – D0 60 SFDR (dBFS) 1V RANGE 55 OGND 50 CLOCK/DUTY 2V RANGE CYCLE 45 CONTROL 40 0 100 200 300 400 500 600 700 800 9001000 224110 TA01 INPUT FREQUENCY (MHz) ENCODE 224110 G11 INPUT 224110fb 1
