LTC2327-16 pin FuncTions VDDLBYP (Pin 1): 2.5V Supply Bypass Pin. The voltage CHAIN (Pin 10): Chain Mode Selector Pin. When low, on this pin is generated via an onboard regulator off of the LTC2327-16 operates in normal mode and the VDD. This pin must be bypassed with a 2.2μF ceramic RDL/SDI input pin functions to enable or disable SDO. capacitor to GND. When high, the LTC2327-16 operates in chain mode and the V RDL/SDI pin functions as SDI, the daisy-chain serial data DD (Pin 2): 5V Power Supply. The range of VDD is 4.75V to 5.25V. Bypass V input. Logic levels are determined by OVDD. DD to GND with a 10µF ceramic capacitor. GND (Pins 3, 6 and 16): Ground. BUSY (Pin 11): BUSY Indicator. Goes high at the start of a new conversion and returns low when the conversion IN+ (Pin 4): Analog Input. IN+ operates differential with has finished. Logic levels are determined by OVDD. respect to IN– with an IN+-IN– range of –2.5 • VREFBUF to 2.5 • V RDL/SDI (Pin 12): When CHAIN is low, the part is in nor- REFBUF. mal mode and the pin is treated as a bus enabling input. IN– (Pin 5): Analog Ground Sense. IN– has an input range When CHAIN is high, the part is in chain mode and the of ±500mV with respect to GND and must be tied to the pin is treated as a serial data input pin where data from ground plane or a remote sense. another ADC in the daisy chain is input. Logic levels are REFBUF (Pin 7): Reference Buffer Output. An onboard determined by OVDD. buffer nominally outputs 4.096V to this pin. This pin is SCK (Pin 13): Serial Data Clock Input. When SDO is enabled, referred to GND and should be decoupled closely to the pin the conversion result or daisy-chain data from another with a 47μF ceramic capacitor. The internal buffer driving ADC is shifted out on the rising edges of this clock MSB this pin may be disabled by grounding its input at REFIN. first. Logic levels are determined by OVDD. Once the buffer is disabled, an external reference may overdrive this pin in the range of 2.5V to 5V. A resistive SDO (Pin 14): Serial Data Output. The conversion result or load greater than 500kΩ can be placed on the reference daisy-chain data is output on this pin on each rising edge buffer output. of SCK MSB first. The output data is in 2’s complement format. Logic levels are determined by OVDD. REFIN (Pin 8): Reference Output/Reference Buffer Input. An onboard bandgap reference nominally outputs 2.048V OVDD (Pin 15): I/O Interface Digital Power. The range of at this pin. Bypass this pin with a 100nF ceramic capacitor OVDD is 1.71V to 5.25V. This supply is nominally set to to GND to limit the reference output noise. If more accu- the same supply as the host interface (1.8V, 2.5V, 3.3V, racy is desired, this pin may be overdriven by an external or 5V). Bypass OVDD to GND with a 0.1μF capacitor. reference in the range of 1.25V to 2.4V. CNV (Pin 9): Convert Input. A rising edge on this input powers up the part and initiates a new conversion. Logic levels are determined by OVDD. 232716fa For more information www.linear.com/LTC2327-16 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Typical Application Related Parts
