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SBAS671 MAY 2014 ADC324x Dual-Channel, 14-Bit, 25 MSPS to 125 MSPS, Analog-to-Digital Converter
1 Features 1 3 Description
The ADC324x are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS, analogto-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is twowire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. Device Information(1)
PART NUMBER ADC324x PACKAGE VQFN (48) BODY SIZE (NOM) 7.00 mm Ч 7.00 mm 2 Applications Multi-Carrier, Multi-Mode Cellular Base Stations Radar and Smart Antenna Arrays Munitions Guidance Motor Control Feedback Network and Vector Analyzers Communications Test Equipment Nondestructive Testing Microwave Receivers Software-Defined Radios (SDRs) Quadrature and Diversity Radio Receivers (1) For all available packages, see the orderable addendum at the end of the datasheet. space space space Performance at fS = 125 MSPS, fIN = 10 MHz
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D001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice. PRODUCT PREVIEW Dual Channel 14-Bit Resolution Single Supply: 1.8 V Serial LVDS Interface (SLVDS) Flexible Input Clock Buffer with Divide-by-1, -2, -4 SNR = 72.4 dBFS, SFDR = 87 dBc at fIN = 70 MHz Ultra-Low Power Consumption: 98 mW/Ch at 125 MSPS Channel Isolation: 105 dB Internal Dither and Chopper Support for Multi-Chip Synchronization Pin-to-Pin Compatible with 12-Bit Version Package: VQFN-48 (7 mm …
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