SLG46620
GreenPAK Programmable Mixed Signal Array
Features Logic & Mixed Signal Circuits Highly Versatile Macro Cells Read Back Protection (Read Lock) 1.8V (±5%) to 5V (±10%) Supply Operating Temperature Range: -40°C to 85°C RoHS Compliant / Halogen-Free 20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch Pin Configuration
GPIO VDD GPI GPIO GPIO GPIO GPIO GPIO GPIO GPIO 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GPIO GPIO GPIO GPIO GPIO GPIO GND Applications Personal Computers and Servers PC Peripherals Consumer Electronics Data Communications Equipment Handheld and Portable Electronics GPIO GPIO GPIO STQFN-20 (Top View) Block Diagram Pin 20 GPIO Pin 1 VDD LF Oscillator Ring Oscillator Pin 19 GPIO RC Oscillator PWR DET Pin 18 GPIO Preliminary Pin 17 GPIO Programmable Delay0 Pin 16 GPIO Counters/Delay Generators ACMP0 Pin 2 GPI CNT5 ACMP1 Pin 3 GPIO DFF/Latches DFF0 ACMP2 Pin 4 GPIO Look Up Tables (LUTs) ACMP3 Pin 5 GPIO ACMP4 Pin 6 GPIO ACMP5 Pin 7 GPIO Pin 8 GPIO PGA 8-bit SAR ADC Pin 9 GPIO DAC0 DAC1 2-bit LUT2_0 2-bit LUT2_5 3-bit LUT3_2 3-bit LUT3_7 3-bit LUT3_12 2-bit LUT2_1 2-bit LUT2_6 3-bit LUT3_3 3-bit LUT3_8 3-bit LUT3_13 2-bit LUT2_2 2-bit LUT2_7 3-bit LUT3_4 3-bit LUT3_9 3-bit LUT3_14 2-bit LUT2_3 3-bit LUT3_0 3-bit LUT3_5 3-bit LUT3_10 3-bit LUT3_15 2-bit LUT2_4 3-bit LUT3_1 3-bit LUT3_6 3-bit LUT3_11 4-bit LUT4_0 DFF6 DFF1 DFF7 DFF2 DFF8 DFF3 DFF9 DFF4 DFF10 DFF5 DFF11 CNT6 CNT7 CNT8 CNT9 CNT0 CNT1 CNT2 CNT3 CNT4 Programmable Delay1 Pin 15 GPIO Pipe Delay0 Vref Pipe Delay1 POR Pin 14 GPIO Additional Logic Functions INV_0 INV_1 Pin 13 GPIO Combination Function Macrocell 4-bit LUT4_1 or PGEN Pin 12 GPIO Pin 11 GND Pin 10 GPIO Silego Technology, Inc. SLG46620_DS_r053 Preliminary Rev 0.53 Revised March 23, 2015 SLG46620
1.0 Overview
The SLG46620 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macro cells of the SLG46620. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macro cells in the device include the following: Six Analog Comparators (ACMP) Voltage References (Vref) with Chopper Sabilized Amplifier Twenty Five Combinatorial Look Up Tables (LUTs) Eight 2-bit LUTs Sixteen 3-bit LUTs One 4-bit LUT One Combination Function Macrocell One Selectable Pattern Generator (PGEN) or 4-bit LUT Ten Counter / Delay Generators (CNT/DLY) Four 14-bit delay/counters Six 8-bit …
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