Datasheet Silicon Labs Si8420BB-D-IS — Даташит

Si8410/20/21
L OW -P OWER S INGLE A N D D UAL -C HANNEL D IGITAL I SOLATORS
Features High-speed operation
DC Up to 2500 VRMS isolation < < 2.1 mA per channel at 1 Mbps 6 mA per channel at 100 Mbps 2.70 V Operation:
< 1.8 mA per channel at 1 Mbps Wide temperature range < 4 mA per channel at 100 Mbps ­40 to 125 °C at 150 Mbps High electromagnetic immunity Applications Industrial automation systems Hybrid electric vehicles Isolated switch mode supplies Safety Regulatory Approvals UL 1577 recognized
Up to 2500 VRMS for 1 minute CSA component notice 5A approval
IEC 60950-1, 61010-1 (reinforced insulation) Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages when compared to legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges throughout their service life. For ease of design, only VDD bypass capacitors are required. Data rates up to 150 Mbps are supported, and all devices achieve worstcase propagation delays of less than 10 ns. All products are safety certified by UL, CSA, and VDE and support withstand voltages of up to 2.5 kVrms. These devices are available in an 8-pin narrow-body SOIC package.
Rev. 1.5 9/13 Copyright © 2013 by Silicon Laboratories Si8410/20/21 N ot fo R r N ec e w om m D e e s nd ig e ns d
2 6 60-year life at rated working No start-up initialization required voltage Wide Operating Supply Voltage: Precise timing (typical) 2.70­5.5 V <10 ns worst case Ultra low power (typical) 1.5 ns pulse width distortion 5 V Operation: 0.5 ns channel-channel skew to 150 Mbps ns propagation delay skew ns minimum pulse width Transient Immunity 25 kV/µs RoHS-compliant packages
SOIC-8 narrow body Ordering Information: See page 25. Isolated ADC, DAC Motor control Power inverters Communications systems VDE certification conformity
IEC 60747-5-2 (VDE0884 Part 2) 2 Si8410/20/21 Rev. 1.5 N ot fo R r N ec e w om m D e e s nd ig e ns d Si8410/20/21 TABLE O F C ONTENTS
Section Page N ot fo R r N ec e w om m D e e s nd ig e ns d
Rev. 1.5 1. Electrical Specifications .4 2. Functional Description . 17 2.1. Theory of Operation . 17 2.2. Eye Diagram . 18 2.3. Device Operation . 19 2.4. Layout Recommendations 20 2.5. Typical Performance Characteristics 21 3. Errata and Design Migration Guidelines . 23 3.1. Power Supply Bypass Capacitors (Revision C and Revision D) 23 3.2. Latch Up Immunity (Revision C Only) 23 4. Pin Descriptions . 24 5. Ordering Guide 25 6. Package Outline …