Sept 13, 2010 W65C22 (W65C22N and W65C22S) Versatile Interface Adapter (VIA) Datasheet WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made to verify the accuracy of the information but no guarantee whatsoever is given as to the accuracy or as to its applicability to particular uses. In every instance, it must be the responsibility of the user to determine the suitability of the products for each application. WDC products are not authorized for use as critical components in life support devices or systems. Nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. Copyright ©1981-2010 by The Western Design Center, Inc. reproduction, in whole or in part, in any form. All rights reserved, including the right of 2 TABLE OF CONTENTS
1. INTRODUCTION. 7 2. W65C22 FUNCTION DESCRIPTION . 8 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 Peripheral Data Ports . 8 Data Transfer -Handshake Control . 10 Read Handshake Control 11 Write Handshake Control 12 Timer 1 Operation . 14 Timer 1 One-Shot Mode . 17 Timer 1 Free-Run Mode . 18 Timer 2 Operation . 19 Timer 2 One-Shot Mode . 19 Timer 2 Pulse Counting Mode . 20 Shift Register Operation . 20 2.12 Shift Register Input Modes . 21 2.12.1 Shift Register Disabled (000) . 21 2.12.2 Shift In -Counter T2 Control (001). 22 2.12.3 Shift In -PHI2 Clock Control (010). 22 2.12.4 Shift In -External CB1 Clock Control (011) . 23 2.13 Shift Register Output Modes . 23 2.13.1 Shift Out -Free Running at T2 Rate (100) . 23 2.13.2 Shift Out -T2 Control (101) . 24 2.13.3 Shift Out -PHI2 Clock Control (110) . 24 2.13.4 Shift Out -External CB1 Clock Control (111) . 25 2.14 Interrupt Operation . 25 3. PIN FUNCTION DESCRIPTION . 28 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 Peripheral Data Port A Control Lines (CA1, CA2) . 30 Peripheral Data Port B Control Lines (CB1, CB2) . 30 Chip Select (CS1, CS2B) . 30 Data Bus (D0-D7) . 31 Interrupt Request (IRQB) . 31 Peripheral Data Port A (PA0-PA7) . 32 Peripheral Data Port B (PB0-PB7) . 34 Phase 2 Internal Clock (PHI2) . 36 Reset (RESB) . 36 Register Select (RS0-RS3) . 36 RWB (Read/Write) . 36 VDD and VSS . 36 3 4. TIMING, AC AND DC CHARACTERISTICS . 37 4.1 4.2 4.3 …
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