74AHC14; 74AHCT14
Hex inverting Schmitt trigger
Rev. 05 -4 May 2009 Product data sheet 1. General description
The 74AHC14; 74AHCT14 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC14; 74AHCT14 provides six inverting buffers with Schmitt-trigger action. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. 2. Features
I I I I Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: N For 74AHC14: CMOS level N For 74AHCT14: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V I Multiple package options I Specified from -40 °C to +85 °C and from -40 °C to +125 °C NXP Semiconductors 74AHC14; 74AHCT14
Hex inverting Schmitt trigger 3. Ordering information
Table 1. Ordering information Package Temperature range Name 74AHC14 74AHC14D 74AHC14PW 74AHC14BQ -40 °C to +125 °C -40 °C to +125 °C -40 °C to +125 °C SO14 TSSOP14 DHVQFN14 plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT108-1 SOT402-1 Description Version Type number plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 Ч 3 Ч 0.85 mm plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT108-1 SOT402-1 74AHCT14 74AHCT14D 74AHCT14PW 74AHCT14BQ -40 °C to +125 °C -40 °C to +125 °C -40 °C to +125 °C SO14 TSSOP14 DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 Ч 3 Ч 0.85 mm 4. Functional diagram 1 2 3 1 1A 1Y 2 5 4 4 3 2A 2Y 6 5 3A 3Y 6 9 8 9 4A 4Y 8 11 10 11 5A 5Y 10 13 12 13 6A 6Y 12 A Y
mna025 mna204 001aac497 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one Schmitt-trigger) 74AHC_AHCT14_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 -4 May 2009 2 of 16 NXP Semiconductors 74AHC14; 74AHCT14
Hex inverting Schmitt trigger 5. Pinning information
5.1 Pinning
terminal 1 index area 1Y 1A 1Y 2A 2Y 3A 3Y GND 1 2 3 4 5 6 7
001aac498 2 3 4 5 6 7 GND 4Y 8 14 VCC 13 6A 12 6Y 11 5A 10 5Y 9 4A 14 VCC 13 6A 12 6Y 2A 2Y 3A 3Y 14 11 5A 10 5Y 9 8 4A 4Y GND(1) 1 1A 14 001aac499 Transparent top view (1) The die substrate is attached to this pad using conductive die at …
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