74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 7 -21 April 2015 Product data sheet 1. General description
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q). The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features and benefits Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: For 74AHC74: CMOS level For 74AHCT74: TTL level ESD protection: HBM EIA/JESD22-A114E exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101C exceeds 1000 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C NXP Semiconductors 74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger 3. Ordering information
Table 1. Ordering information Package Temperature range 74AHC74 74AHC74D 74AHC74PW 74AHC74BQ 40 C to +125 C 40 C to +125 C 40 C to +125 C SO14 TSSOP14 plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT108-1 SOT402-1 SOT762-1 Name Description Version Type number DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm SO14 TSSOP14 plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74AHCT74 74AHCT74D 74AHCT74PW 74AHCT74BQ 40 C to +125 C 40 C to +125 C 40 C to +125 C SOT108-1 SOT402-1 SOT762-1 DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm 4. Functional diagram
4 10 1SD 2SD 2 12 3 11 SD 1Q 1D Q D 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 1RD 2RD 1 13
mna418 5 9 6 8 Fig 1. Functional diagram 74AHC_AHCT74 All information provided in this document is subject to legal disclaimers. © NXP Semiconducto …
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