Datasheet ТI SN74LVC2G126DCUT — Даташит

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Documents SN74LVC2G126
SCES205M – APRIL 1999 – REVISED SEPTEMBER 2016 SN74LVC2G126 Dual Bus Buffer Gate With 3-State Outputs
1 Features 2 Applications 1 Available in the Texas Instruments NanoFreeв„ў
Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4ns at 3.3V
Low Power Consumption, 10-ВµA Max ICC
В±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25В°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25В°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate
Inputs From a Max of 5.5 V Down to the VCC
Level …