Datasheet Texas Instruments TMS320C80GF — Даташит

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Купить TMS320C80GF на РадиоЛоцман.Цены — от 65 до 1 394 187 ₽ 19 предложений от 18 поставщиков Процессоры и контроллеры цифровых сигналов (DSP, DSC) TMS320C80 - 305pin cBGA - 60 MHz, PG5.1
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Статус

Корпус / Упаковка / Маркировка

Экологический статус

Application Notes

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  Implementing an MPEG2 Video Decoder Based on the TMS320C80 MVP
  PDF, 168 Кб, Файл опубликован: 1 июл 1997
  This application report presents the preliminary results obtained in the realization of the MPEG2 video decoder on the Texas Instruments (TI(TM)) TM532OC80 MVP. We have addressed and solved the problems of bitstream scanning, variable-length code decoding, and inverse discrete cosine transform (DCT). The results obtained, integrated with preliminary work and available information about time requir
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  TMS320C80 Frame Buffer
  PDF, 446 Кб, Файл опубликован: 28 фев 1997
  The TMS320C80 ('C80) is a 32-bit multiprocessor digital signal processor (DSP) that provides direct support of two independent frame memories through on-chip controllers. This document presents a 4M-byte video random access memory (VRAM) based frame buffer interface to the 'C80 DSP. An in-depth discussion of the hardware interface for the frame buffer card palette, a VRAM overview, and information
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  H.261 Implementation on the TMS320C80 DSP
  PDF, 135 Кб, Файл опубликован: 1 июн 1997
  This report describes the coding requirements, techniques, and decisions whichmust be made to utilize the TMS320C80 DSP as an integrated services digitalnetwork (ISDN) video-system manager and provides an overview on how theprocessor handles video signal in the ISDN narrow-band format in conformancewith the International Telecommunications Union (ITU)?T H.261 Recommendation.
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  Parallelization of a H.263 Encoder for the TMS320C80 MVP
  PDF, 270 Кб, Файл опубликован: 1 июл 1997
  The coding of digital video sequences has been paid increasing attention over the past few years. Algorithms and standards such as MPEG1, MPEG2 or H.261 have been developed allowing more and more compression. A new standard in this field is H.263 which has been recently adopted by the ITU. It is intended for videoconferencing, videophoning, surveillance and other low bit rate applications (below 2
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  Color-Space Format Conversion Using the TMS320C80 Transfer Controller
  PDF, 98 Кб, Файл опубликован: 1 мар 1998
  This application report describes the conversion of color-picture data from themacroblock (MB) format used by ITU-T Recommendation H.261 to the format usedby the Texas Instruments (TIE) TMS320C80 family of digital signal processors(DSPs). Conversion is necessary in some instances because of the differencebetween the MB format and the TI format and the necessity of the ?C80 to maintain co
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  Interfacing DRAM to the TMS320C80 DSP
  PDF, 301 Кб, Файл опубликован: 1 июл 1996
  The TMS320C80 ('C80) 32-bit multiprocessor digital signal processor (DSP) contains DRAM support in its memory interface. This document provides a DRAM functional description, describes the 'C80 address subcycles, and shows a DRAM system overview. The appendix provides a bill of materials, schematics, and ABEL files for this interface application.
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  Radix-4 Decimation in Frequency (DIF) Fast Fourier Transform (FFT)-TMS320C80
  PDF, 141 Кб, Файл опубликован: 1 авг 1996
  This application report describes the implementation of the radix-4 decimation in frequency (DIF) fast Fourier transform (FFT) algorithm using the Texas Instruments (TI(TM)) TMS320C80 digital signal processor (DSP). The radix-4 DIF algorithm increases the execution speed of the FFT.Each TMS320C80 DSP parallel processor (PP) contains four major units operating in parallel. This parallel operati
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  Interfacing Synchronous DRAM to the TMS320C80 Parallel DSP
  PDF, 273 Кб, Файл опубликован: 1 авг 1996
  The parallel architecture of the 32-bit multiprocessor TMS320C80 ('C80) digital signal processor (DSP) offers incredible horsepower that is underutilized without a high-speed memory interface. The 'C80 contains a built-in interface for SDRAM. This document discusses the interface between the 'C80 and the TMS626802-10 SDRAM, the SDRAM pins, and the SDRAM operation. A timing evaluation of the inter
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  Faster Scan Conversion Using the TMS320C80 DSP
  PDF, 146 Кб, Файл опубликован: 1 июл 1997
  This application report describes the process of parallelizing the scan conversion stage using the Texas Instruments (TI(TM)) TMS320C80 digital signal processor (DSP). Current approaches are discussed and a new approach is suggested to make the graphics pipeline faster, especially at the scan conversion stage. The suitability of the TMS320C80 for the suggested approach is investigated and the desi
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  Acoustic Echo Cancellation Algorithms and Implementation on the TMS320C80
  PDF, 223 Кб, Файл опубликован: 1 май 1996
  Acoustic echo cancellation on the TMS320C8x multiprocessor digital signal processor (DSP) offers high performance and flexibility to meet varying user needs. This document describes the implementation of an integrated N-tap digital acoustic echo canceller on the TMS320C8x parallel processor (PP). A brief discussion of a generic echo cancellation algorithm is provided. A 512-tap (64-ms span) echo
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  TMS320C8x System-Level Synopsis (Rev. B)
  PDF, 516 Кб, Версия: B, Файл опубликован: 1 сен 1995
  The TMS320C8x is Texas Instruments? first generation of single-chipmultiprocessor digital signal processor (DSP) devices. Asingle ?C8x contains up to five powerful, fully programmable pro-cessors:a master processor (MP) and up to four parallel proces-sors(PPs). The MP is a 32-bit RISC (reduced instruction setcomputer) processor with an integral, high-performanceIEEE-754 floating-point
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  Modified Goertzel Algorithm in DTMF Detection Using the TMS320C80 DSP
  PDF, 101 Кб, Файл опубликован: 1 июн 1996
  This document presents a modified Goertzel algorithm for DTMF tone detection on a TMS320C80 ('C80) 32-bit multiprocessor digital signal processor (DSP). The algorithm detects the incoming frequency with an offset range plus or minus 1.5%. For this application, a basic implementation is provided, but additional testing is required to make this detection algorithm complete. The appendix provides the
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  Linking C Data Objects Separate from the .bss Section
  PDF, 40 Кб, Файл опубликован: 1 июн 1997
  The TMS320 DSP C compilers produce several relocatable blocks of code and data when C code is compiled. These blocks are called sections and can be allocated into memory in a variety of ways to conform to a variety of system configurations. The .bss section is used by the compiler for global and static variables. It is one of the default COFF sections that is used to reserve a specified amount of

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• Semiconductors > Processors > Other Processors