Datasheet ТI SN74LVCH32374AGKER — Даташит

SN74LVCH32374A
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS www.ti.com SCAS619E – OCTOBER 1998 – REVISED AUGUST 2007 FEATURES 1 Member of the Texas Instruments Widebus+™
Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.5 ns at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25В°C Typical VOHV (Output VOH Undershoot) > 2 V
at VCC = 3.3 V, TA = 25В°C
2 Ioff Supports Partial-Power-Down Mode
Operation
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input and Output Voltages With
3.3-V VCC)
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17 DESCRIPTION/ORDERING INFORMATION
This 32-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCH32374A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On
the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the
data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines …