[ /Title
(CD74
HC402
4,
CD74
HCT40
24)
/Subject
(High
Speed
CMOS CD54HC4024, CD74HC4024,
CD54HCT4024, CD74HCT4024
Data sheet acquired from Harris Semiconductor
SCHS202C High-Speed CMOS Logic
7-Stage Binary Ripple Counter November 1997 -Revised October 2003 Features Description Fully Static Operation The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary
counters. All counter stages are master-slave flip-flops. The
state of the stage advances one count on the negative
transition of each input pulse; a high voltage level on the MR
line resets all counters to their zero state. All inputs and
outputs are buffered. Buffered Inputs Common Reset Negative Edge Clocking Fanout (Over Temperature Range) Ordering Information -Standard Outputs . 10 LSTTL Loads
-Bus Driver Outputs . 15 LSTTL Loads PART NUMBER Wide Operating Temperature Range . -55oC to 125oC TEMP. RANGE
(oC) PACKAGE Balanced Propagation Delay and Transition Times CD54HC4024F3A -55 to 125 14 Ld CERDIP Significant Power Reduction Compared to LSTTL
Logic ICs CD54HCT4024F3A -55 to 125 14 Ld CERDIP CD74HC4024E -55 to 125 14 Ld PDIP CD74HC4024M -55 to 125 14 Ld SOIC CD74HC4024MT -55 to 125 14 Ld SOIC CD74HC4024M96 -55 to 125 14 Ld SOIC CD74HC4024PW -55 to 125 14 Ld TSSOP CD74HC4024PWR -55 to 125 14 Ld TSSOP CD74HC4024PWT -55 to 125 14 Ld TSSOP CD74HCT4024E -55 to 125 14 Ld PDIP CD74HCT4024M -55 to 125 14 Ld SOIC HC Types …
