[ /Title
(CD74
HC402
0,
CD74
HCT40
20)
/Subject
(High
Speed
CMOS CD54HC4020, CD74HC4020,
CD54HCT4020, CD74HCT4020
Data sheet acquired from Harris Semiconductor
SCHS201C High-Speed CMOS Logic
14-Stage Binary Counter February 1998 -Revised October 2003 Features Description Fully Static Operation The ’HC4020 and ’HCT4020 are 14-stage ripple-carry
binary counters. All counter stages are master-slave flipflops. The state of the stage advances one count on the
negative clock transition of each input pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered. Buffered Inputs Common Reset Negative Edge Clocking Fanout (Over Temperature Range) Ordering Information -Standard Outputs . 10 LSTTL Loads
-Bus Driver Outputs . 15 LSTTL Loads PART NUMBER Wide Operating Temperature Range . -55oC to 125oC TEMP. RANGE
(oC) PACKAGE Balanced Propagation Delay and Transition Times CD54HC4020F3A -55 to 125 16 Ld CERDIP Significant Power Reduction Compared to LSTTL
Logic ICs CD54HCT4020F3A -55 to 125 16 Ld CERDIP CD74HC4020E -55 to 125 16 Ld PDIP CD74HC4020M -55 to 125 16 Ld SOIC CD74HC4020MT -55 to 125 16 Ld SOIC CD74HC4020M96 -55 to 125 16 Ld SOIC CD74HCT4020E -55 to 125 16 Ld PDIP CD74HCT4020M -55 to 125 16 Ld SOIC CD74HCT4020MT -55 to 125 16 Ld SOIC CD74HCT4020M96 -55 to 125 16 Ld SOIC HC Types
-2V to 6V Operation …
