Datasheet Texas Instruments ADS5521IPAPR — Даташит
| Производитель | Texas Instruments |
| Серия | ADS5521 |
| Модель | ADS5521IPAPR |
12-разрядный аналого-цифровой преобразователь (АЦП) с быстродействием 105 MSPS 64-HTQFP от -40 до 85
Datasheets
12-Bit, 105MSPS Analog-to-Digital Converter datasheet
PDF, 689 Кб, Версия: D, Файл опубликован: 30 окт 2008
Выписка из документа
Цены
 Купить ADS5521IPAPR на РадиоЛоцман.Цены — от 72 до 3 855 ₽12 предложений от 9 поставщиков 12Bit, 105MSPS Analog-to-Digital Converter (ADC) 64-HTQFP -40℃ to 85℃ | |||
| ADS5521IPAPR Texas Instruments | 72 ₽ | ||
| ADS5521IPAPR Texas Instruments | от 3 245 ₽ | ||
| ADS5521IPAPR Texas Instruments | 3 624 ₽ | ||
| ADS5521IPAPR Texas Instruments | по запросу | ||
Статус
| Статус продукта | Снят с производства (Производитель прекратил производство прибора) |
| Доступность образцов у производителя | Нет |
Корпус / Упаковка / Маркировка
| Pin | 64 |
| Package Type | PAP |
| Industry STD Term | HTQFP |
| JEDEC Code | S-PQFP-G |
| Width (мм) | 10 |
| Length (мм) | 10 |
| Thickness (мм) | 1 |
| Pitch (мм) | .5 |
| Max Height (мм) | 1.2 |
| Mechanical Data | Скачать |
Параметры
| # Input Channels | 1 |
| Analog Input BW(MHz) | 750 |
| Approx. Price (US$) | 36.79 | 1ku |
| Архитектура | Pipeline |
| DNL(Max)(+/-LSB) | 0.25 |
| ENOB(Bits) | 11.3 |
| INL(Max)(+/-LSB) | 0.5 |
| Input Buffer | No |
| Input Range | 2.3V (p-p) |
| Interface | Parallel CMOS Serial SPI Interface |
| Operating Temperature Range(C) | -40 to 85 |
| Package Group | HTQFP |
| Package Size: mm2:W x L (PKG) | 64HTQFP: 144 mm2: 12 x 12(HTQFP) |
| Power Consumption(Typ)(mW) | 736 |
| Rating | Catalog |
| Reference Mode | Int |
| Resolution(Bits) | 12 |
| SFDR(dB) | 86 |
| SINAD(dB) | 70 |
| SNR(dB) | 70.5 |
| Sample Rate(Max)(MSPS) | 105 |
Экологический статус
| RoHS | Не совместим |
| Бессвинцовая технология (Pb Free) | Нет |
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Статус продукта: В производстве (Рекомендуется для новых разработок)
Application Notes
- Clocking High-Speed Data ConvertersPDF, 310 Кб, Файл опубликован: 18 янв 2005
- Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Мб, Версия: A, Файл опубликован: 22 май 2015
- Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Мб, Версия: A, Файл опубликован: 19 июл 2013
- Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Кб, Файл опубликован: 28 апр 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Кб, Версия: A, Файл опубликован: 10 сен 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Мб, Файл опубликован: 2 июн 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Кб, Файл опубликован: 8 июн 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Interleaving Analog-to-Digital ConvertersPDF, 64 Кб, Файл опубликован: 2 окт 2000
It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration several possible sources of error. - A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Кб, Версия: B, Файл опубликован: 9 окт 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Кб, Версия: A, Файл опубликован: 16 апр 2015
- Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Кб, Версия: A, Файл опубликован: 18 май 2015
- What Designers Should Know About Data Converter DriftPDF, 95 Кб, Файл опубликован: 2 окт 2000
Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its operating-temperature extremes, perhaps only to 9 or even 8 bits. But for lack of more precise knowledge, many play it safe (and expensive) and overspecify.
Модельный ряд
Серия: ADS5521 (3)
- ADS5521IPAP ADS5521IPAPR ADS5521IPAPRG4
Классификация производителя
- Semiconductors > Data Converters > Analog to Digital Converter > High Speed ADC (>10MSPS)
