Datasheet ТI CD74HCT107E — Даташит

[ /Title
(CD74
HC107
,
CD74
HCT10
7)
/Subject
(Dual
J-K
FlipFlop
with
Reset
Negative-CD54HC107, CD74HC107,
CD74HCT107
Data sheet acquired from Harris Semiconductor
SCHS139D Dual J-K Flip-Flop with Reset
Negative-Edge Trigger March 1998 -Revised October 2003 Features Description Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times The ’HC107 and CD74HCT107 utilize silicon gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads. Asynchronous Reset Complementary Outputs These flip-flops have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the …