Datasheet ТI SN74F109DRG4 — Даташит

SN54F109, SN74F109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS047A – MARCH 1987 – REVISED OCTOBER 1993 SN54F109 . J PACKAGE
SN74F109 . D OR N PACKAGE
(TOP VIEW) Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs 1CLR
1J
1K
1CLK
1PRE
1Q
1Q
GND description
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K input meeting the
setup-time requirements are transferred to the …