SN74LV125A-Q1
www.ti.com SCES814 – SEPTEMBER 2010 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
Check for Samples: SN74LV125A-Q1 FEATURES 1 1A
1Y
2OE
2A
2Y VCC RGY PACKAGE
(TOP VIEW) 1 14 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE
9 3A 6 GND 7 8 3Y Qualified for Automotive Applications
2-V to 5.5-V VCC Operation
Typical VOLP (Output Ground Bounce)
2.3 V at VCC = 3.3 V, TA = 25В°C
Support Mixed-Mode Voltage Operation on All
Ports
Ioff Supports Partial-Power-Down Mode
Operation 1OE DESCRIPTION
The SN74LV125A-Q1 quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.
This device features independent line drivers with 3-state outputs. Each output is disabled when the associated
output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down. …
