CD4094BMS
CMOS 8-Stage Shift-and-Store
Bus Register December 1992 Features Pinout High Voltage Type (20V Rating) CD4094BMS
TOP VIEW 3-State Parallel Outputs for Connection to Common
Bus Separate Serial Outputs Synchronous to Both Positive
and Negative Clock Edges for Cascading 16 VDD STROBE 1 Medium Speed Operation -5MHz at 10V (typ) 15 OUTPUT ENABLE DATA 2 Standardized Symmetrical Output Characteristics CLOCK 3 14 Q5 100% Tested for Quiescent Current at 20V Q1 4 13 Q6 Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC Q2 5 12 Q7 Q3 6 11 Q8 Q4 7 10 Q’S VSS 8 9 QS Noise Margin (Over Full Package/Temperature Range)
-1V at VDD = 5V
-2V at VDD = 10V
-2.5V at VDD = 15V 5V, 10V and 15V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
�B’ Series CMOS Devices” Functional Diagram Applications Serial-to-Parallel Data Conversion Remote Control Holding Register DATA 2 CLOCK 3 STROBE 1 OUTPUT
ENABLE 15 Dual-Rank Shift, Hold, and Bus Applications SERIAL
OUTPUTS
10 Q’S
8-STAGE
SHIFT
REGISTER 9 QS Description
CD4094BMS is a 8-stage serial shift register having a storage
latch associated with each stage for strobing data from the serial
input to parallel buffered 3-state outputs. The parallel outputs
may be connected directly to common bus lines. Data is shifted
on positive clock transitions. The data in each shift register stage
is transferred to the storage register when the STROBE input is …
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