Datasheet Texas Instruments ADS41B25 — Даташит
| Производитель | Texas Instruments |
| Серия | ADS41B25 |
12-битный аналого-цифровой преобразователь (АЦП) с быстродействием 125 MSPS
Datasheets
12-Bit, 125MSPS Ultra-Low Power ADC with Analog Buffer datasheet
PDF, 1.6 Мб, Файл опубликован: 22 июн 2011
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Статус
| ADS41B25IRGZR | ADS41B25IRGZT | |
|---|---|---|
| Статус продукта | В производстве | В производстве |
| Доступность образцов у производителя | Нет | Да |
Корпус / Упаковка / Маркировка
| ADS41B25IRGZR | ADS41B25IRGZT | |
|---|---|---|
| N | 1 | 2 |
| Pin | 48 | 48 |
| Package Type | RGZ | RGZ |
| Industry STD Term | VQFN | VQFN |
| JEDEC Code | S-PQFP-N | S-PQFP-N |
| Package QTY | 2500 | 250 |
| Carrier | LARGE T&R | SMALL T&R |
| Маркировка | AZ41B25 | AZ41B25 |
| Width (мм) | 7 | 7 |
| Length (мм) | 7 | 7 |
| Thickness (мм) | .9 | .9 |
| Pitch (мм) | .5 | .5 |
| Max Height (мм) | 1 | 1 |
| Mechanical Data | Скачать | Скачать |
Параметры
| Parameters / Models | ADS41B25IRGZR | ADS41B25IRGZT |
|---|---|---|
| # Input Channels | 1 | 1 |
| Analog Input BW, МГц | 800 | 800 |
| Архитектура | Pipeline | Pipeline |
| DNL(Typ), +/-LSB | 1.5 | 1.5 |
| ENOB, Bits | 11.1 | 11.1 |
| INL(Max), +/-LSB | 3.5 | 3.5 |
| INL(Typ), +/-LSB | 1.5 | 1.5 |
| Input Buffer | Yes | Yes |
| Input Range, Vp-p | 1.5 | 1.5 |
| Interface | DDR LVDS,Parallel CMOS | DDR LVDS,Parallel CMOS |
| Рабочий диапазон температур, C | от -40 до 85 | от -40 до 85 |
| Package Group | VQFN | VQFN |
| Package Size: mm2:W x L, PKG | 48VQFN: 49 mm2: 7 x 7(VQFN) | 48VQFN: 49 mm2: 7 x 7(VQFN) |
| Power Consumption(Typ), mW | 310 | 310 |
| Rating | Catalog | Catalog |
| Reference Mode | Int | Int |
| Разрешение, Bits | 12 | 12 |
| SFDR, дБ | 89 | 89 |
| SINAD, дБ | 68.8 | 68.8 |
| SNR, дБ | 68.8 | 68.8 |
| Sample Rate(Max), MSPS | 125 | 125 |
Экологический статус
| ADS41B25IRGZR | ADS41B25IRGZT | |
|---|---|---|
| RoHS | Совместим | Совместим |
Application Notes
- High-Speed Analog-to-Digital Converter BasicsPDF, 1.1 Мб, Файл опубликован: 11 янв 2012
The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil - Band-Pass Filter Design Techniques for High-Speed ADCsPDF, 733 Кб, Файл опубликован: 27 фев 2012
Several well-known methods exist for designing passive inductor-capacitor (LC) filters with resistive load terminations. However, when LC filters are used to drive the analog input pins of a high-speed analog-to-digital converter (ADC), special consideration must be given to the ADC input impedance. Not accounting for the ADC input impedance often results in a filter design that does not meet the - QFN Layout GuidelinesPDF, 1.3 Мб, Файл опубликован: 28 июл 2006
Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs. - CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Кб, Файл опубликован: 4 сен 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Мб, Версия: A, Файл опубликован: 19 июл 2013
- Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Мб, Версия: A, Файл опубликован: 22 май 2015
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Мб, Файл опубликован: 2 июн 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Кб, Файл опубликован: 8 июн 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Кб, Версия: A, Файл опубликован: 16 апр 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Кб, Версия: B, Файл опубликован: 9 окт 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Кб, Версия: A, Файл опубликован: 18 май 2015
Модельный ряд
Серия: ADS41B25 (2)
Классификация производителя
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
