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Datasheet Texas Instruments ADS6142

ПроизводительTexas Instruments

14-Bit, 65-MSPS Analog-to-Digital Converter (ADC)


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  • Скачать » Datasheet PDF, 2.3 Мб, Версия: B, Файл опубликован: 4 дек 2007
    14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS datasheet
    Выписка из документа ↓
    ADS6145, ADS6144
    ADS6143, ADS6142 www.ti.com SLWS198B – JULY 2007 – REVISED MARCH 2008 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS FEATURES 1 Maximum Sample Rate: 125 MSPS
    14-Bit Resolution with No Missing Codes
    3.5 dB Coarse Gain and up to 6 dB
    Programmable Fine Gain for SNR/SFDR
    Parallel CMOS and Double Data Rate (DDR)
    LVDS Output Options
    Supports Sine, LVCMOS, LVPECL, LVDS Clock
    Inputs, and Clock Amplitude Down to 400
    Clock Duty Cycle Stabilizer
    Internal Reference with Support for External
    No External Decoupling Required for
    Programmable Output Clock Position and
    Drive Strength to Ease Data Capture
    3.3-V Analog and 1.8-V to 3.3-V Digital Supply
    32-QFN Package (5 mm Г— 5 mm)
    Pin Compatible 12-Bit Family (ADS612X) APPLICATIONS Radar Systems DESCRIPTION
    ADS6145/ADS6144/ADS6143/ADS6142 (ADS614X)
    are a family of 14-bit A/D converters with sampling ...


Single Channel Single ADC Pipelined 65Msps 14-bit Serial (3-Wire)/LVDS 32-Pin VQFN EP T/R
AllchipsTexas InstrumentsADS6142IRHBT2 133 руб.
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Семейство: ADS6142, ADS6143, ADS6144, ADS6145


Статус продуктаВ производствеВ производствеВ производстве
Доступность образцов у производителяНетНетНет

Корпус / Упаковка / Маркировка

Package QTY3000250250
Width (мм)555
Length (мм)555
Thickness (мм).9.9.9
Pitch (мм).5.5.5
Max Height (мм)111
Mechanical DataСкачать »Скачать »Скачать »


# Input Channels111
Analog Input BW, МГц500500
Analog Input BW(MHz)500
Approx. Price (US$)20.50 | 1ku
DNL(Max), +/-LSB22
DNL(Typ), +/-LSB0.50.5
ENOB, Bits1212
INL(Max), +/-LSB44
INL(Typ), +/-LSB22
Input BufferNoNo
Input Range222V (p-p)
InterfaceDDR LVDS,Parallel CMOSDDR LVDS,Parallel CMOSParallel LVDS
Serial SPI Interface
Рабочий диапазон температур, Cот -40 до 85от -40 до 85
Operating Temperature Range(C)-40 to 85
Package Size(mm2=WxL)32VQFN: 25 mm2: 5 x 5
Package Size: mm2:W x L, PKG32VQFN: 25 mm2: 5 x 5(VQFN)32VQFN: 25 mm2: 5 x 5(VQFN)
Power Consumption(Typ), mW285285
Power Consumption(Typ)(mW)285
Reference ModeExt,IntExt,IntExt
Разрешение, Bits1414
SFDR, дБ8686
SINAD, дБ74.474.4
SNR, дБ74.674.6
Sample Rate (max)(SPS)65MSPS
Sample Rate(Max), MSPS6565

Экологический статус

Бессвинцовая технология (Pb Free)Да

Application Notes

  • Скачать » Application Notes PDF, 733 Кб, Файл опубликован: 27 фев 2012
    Band-Pass Filter Design Techniques for High-Speed ADCs
    Several well-known methods exist for designing passive inductor-capacitor (LC) filters with resistive load terminations. However, when LC filters are used to drive the analog input pins of a high-speed analog-to-digital converter (ADC), special consideration must be given to the ADC input impedance. Not accounting for the ADC input impedance often results in a filter design that does not meet the
  • Скачать » Application Notes PDF, 1.3 Мб, Файл опубликован: 28 июл 2006
    QFN Layout Guidelines
    Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
  • Скачать » Application Notes PDF, 805 Кб, Файл опубликован: 4 сен 2008
    CDCE62005 as Clock Solution for High-Speed ADCs
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Скачать » Application Notes PDF, 1.2 Мб, Версия: A, Файл опубликован: 19 июл 2013
    Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  • Скачать » Application Notes PDF, 2.0 Мб, Версия: A, Файл опубликован: 22 май 2015
    Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  • Скачать » Application Notes PDF, 376 Кб, Файл опубликован: 28 апр 2009
    Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Скачать » Application Notes PDF, 327 Кб, Версия: A, Файл опубликован: 10 сен 2010
    Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Скачать » Application Notes PDF, 2.3 Мб, Файл опубликован: 2 июн 2008
    Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • Скачать » Application Notes PDF, 424 Кб, Файл опубликован: 8 июн 2008
    CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Скачать » Application Notes PDF, 132 Кб, Версия: A, Файл опубликован: 16 апр 2015
    Principles of Data Acquisition and Conversion (Rev. A)
  • Скачать » Application Notes PDF, 425 Кб, Версия: B, Файл опубликован: 9 окт 2011
    A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Скачать » Application Notes PDF, 69 Кб, Версия: A, Файл опубликован: 18 май 2015
    Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)

Модельный ряд

Серия: ADS6142 (3)

Классификация производителя

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)

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