Datasheet Texas Instruments ADS6423 — Даташит

Производитель	Texas Instruments
Серия	ADS6423

Datasheets

Цены

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EIS Components Весь мир	ADS6423IRGCR Texas Instruments	66 ₽	Купить
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Augswan Весь мир	ADS6423IRGCT Texas Instruments	по запросу	Купить
ЭлектроПласт- Екатеринбург Россия	ADS6423IRGCTG4 Texas Instruments	по запросу	Купить

Статус

Корпус / Упаковка / Маркировка

Параметры

Parameters / Models	ADS6423IRGCT
# Input Channels	4
Analog Input BW, МГц	500
Архитектура	Pipeline
DNL(Max), +/-LSB	1.8
DNL(Typ), +/-LSB	0.4
ENOB, Bits	11.5
INL(Max), +/-LSB	2
INL(Typ), +/-LSB	1.25
Input Buffer	No
Input Range, Vp-p	2
Interface	Serial LVDS
Рабочий диапазон температур, C	от -40 до 85
Package Group	VQFN
Package Size: mm2:W x L, PKG	64VQFN: 81 mm2: 9 x 9(VQFN)
Power Consumption(Typ), mW	1180
Rating	Catalog
Reference Mode	Ext,Int
Разрешение, Bits	12
SFDR, дБ	87
SINAD, дБ	70.9
SNR, дБ	70.9
Sample Rate(Max), MSPS	80

Экологический статус

Application Notes

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  Band-Pass Filter Design Techniques for High-Speed ADCs
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  Several well-known methods exist for designing passive inductor-capacitor (LC) filters with resistive load terminations. However, when LC filters are used to drive the analog input pins of a high-speed analog-to-digital converter (ADC), special consideration must be given to the ADC input impedance. Not accounting for the ADC input impedance often results in a filter design that does not meet the
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  QFN Layout Guidelines
  PDF, 1.3 Мб, Файл опубликован: 28 июл 2006
  Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
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  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Кб, Файл опубликован: 4 сен 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
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  Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  PDF, 2.0 Мб, Версия: A, Файл опубликован: 22 май 2015
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  Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
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  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Кб, Файл опубликован: 28 апр 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
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  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Кб, Версия: A, Файл опубликован: 10 сен 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
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  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Мб, Файл опубликован: 2 июн 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Кб, Файл опубликован: 8 июн 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
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  QFN and SON PCB Attachment (Rev. B)
  PDF, 821 Кб, Версия: B, Файл опубликован: 24 авг 2018
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  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Кб, Версия: A, Файл опубликован: 16 апр 2015
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  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Кб, Версия: B, Файл опубликован: 9 окт 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
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  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Кб, Версия: A, Файл опубликован: 18 май 2015

Модельный ряд

Классификация производителя

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)