Datasheet Texas Instruments ADS930 — Даташит
| Производитель | Texas Instruments |
| Серия | ADS930 |
8-Bit, 30 MSPS ADC SE/Diff Inputs w/ Internal Ref. and Low Power, Powerdown
Datasheets
ADS930: SpeedPlus? 8-Bit, 30MHz Sampling Analog-To-Digital Converter datasheet
PDF, 416 Кб, Версия: A, Файл опубликован: 23 фев 2001
Выписка из документа
ADS930: SpeedPlus? 8-Bit, 30MHz Sampling Analog-To-Digital Converter (Rev. A)
PDF, 416 Кб, Версия: A, Файл опубликован: 23 фев 2001
Цены
 Купить ADS930 на РадиоЛоцман.Цены — от 264 до 29 351 ₽35 предложений от 25 поставщиков АЦП, 8 бит, 30 Мвыборок/с, Дифференциальный, Несимметричный, Параллельный, Однополярный, 2.7 В | |||
| ADS930E/1K Texas Instruments | 264 ₽ | ||
| ADS930E/1KG4 Texas Instruments | от 340 ₽ | ||
| ADS930E SSOP28 BB | 704 ₽ | ||
| ADS930EG4 Texas Instruments | по запросу | ||
Статус
| ADS930E | ADS930E/1K | ADS930E/1KG4 | |
|---|---|---|---|
| Статус продукта | В производстве | В производстве | В производстве |
| Доступность образцов у производителя | Нет | Нет | Нет |
Корпус / Упаковка / Маркировка
| ADS930E | ADS930E/1K | ADS930E/1KG4 | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 28 | 28 | 28 |
| Package Type | DB | DB | DB |
| Industry STD Term | SSOP | SSOP | SSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 50 | 1000 | 1000 |
| Carrier | TUBE | LARGE T&R | LARGE T&R |
| Маркировка | ADS930E | ADS930E | ADS930E |
| Width (мм) | 5.3 | 5.3 | 5.3 |
| Length (мм) | 10.2 | 10.2 | 10.2 |
| Thickness (мм) | 1.95 | 1.95 | 1.95 |
| Pitch (мм) | .65 | .65 | .65 |
| Max Height (мм) | 2 | 2 | 2 |
| Mechanical Data | Скачать | Скачать | Скачать |
Параметры
| Parameters / Models | ADS930E | ADS930E/1K | ADS930E/1KG4 |
|---|---|---|---|
| # Input Channels | 1 | 1 | 1 |
| Analog Input BW, МГц | 100 | 100 | |
| Analog Input BW(MHz) | 100 | ||
| Approx. Price (US$) | 3.12 | 1ku | ||
| Архитектура | Pipeline | Pipeline | Pipeline |
| DNL(Max), +/-LSB | 1 | 1 | |
| DNL(Max)(+/-LSB) | 1 | ||
| DNL(Typ), +/-LSB | 0.4 | 0.4 | |
| ENOB, Bits | 7.1 | 7.1 | |
| ENOB(Bits) | 7.1 | ||
| INL(Max), +/-LSB | 2.5 | 2.5 | |
| INL(Max)(+/-LSB) | 2.5 | ||
| INL(Typ), +/-LSB | 1 | 1 | |
| Input Buffer | No | No | |
| Input Range | 1,2 | 1,2 | 1V / 2V (p-p) |
| Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Рабочий диапазон температур, C | от -40 до 85 | от -40 до 85 | |
| Package Group | SSOP | SSOP | SSOP |
| Package Size(mm2=WxL) | 28SSOP: 80 mm2: 7.8 x 10.2 | ||
| Package Size: mm2:W x L, PKG | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) | |
| Power Consumption(Typ), mW | 66 | 66 | |
| Power Consumption(Typ)(mW) | 66 | ||
| Rating | Catalog | Catalog | Catalog |
| Reference Mode | Ext,Int | Ext,Int | Int Ext |
| Разрешение, Bits | 8 | 8 | |
| Resolution(Bits) | 8 | ||
| SFDR, дБ | 50 | 50 | |
| SFDR(dB) | 50 | ||
| SINAD, дБ | 45 | 45 | |
| SINAD(dB) | 45 | ||
| SNR, дБ | 46 | 46 | |
| SNR(dB) | 46 | ||
| Sample Rate (max)(SPS) | 30MSPS | ||
| Sample Rate(Max), MSPS | 30 | 30 |
Экологический статус
| ADS930E | ADS930E/1K | ADS930E/1KG4 | |
|---|---|---|---|
| RoHS | Совместим | Совместим | TBD |
| Бессвинцовая технология (Pb Free) | Нет |
Application Notes
- CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Кб, Файл опубликован: 4 сен 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Кб, Файл опубликован: 28 апр 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Кб, Версия: A, Файл опубликован: 10 сен 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Мб, Файл опубликован: 2 июн 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Кб, Файл опубликован: 8 июн 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
Модельный ряд
Серия: ADS930 (3)
Классификация производителя
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
