Datasheet ТI CD74ACT280 — Даташит

CD54/74AC280,
CD54/74ACT280
Data sheet acquired from Harris Semiconductor
SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 -Revised May 2000 Features data inputs is HIGH. Odd parity is indicated (∑O output is
HIGH) when an odd number of data inputs is HIGH. Parity
checking for words larger than nine bits can be accomplished by tying the ∑E output to any input of an additional
’AC280, ’ACT280 parity checker. Buffered Inputs Typical Propagation Delay
-10ns at VCC = 5V, TA = 25oC, CL = 50pF Exceeds 2kV ESD Protection per MIL-STD-883,
Method 3015 Ordering Information
PART
NUMBER SCR-Latchup-Resistant CMOS Process and Circuit
Design TEMP.
RANGE (oC) CD54AC280F3A Speed of Bipolar FASTв„ў/AS/S with Significantly
Reduced Power Consumption -55 to 125 14 Ld CERDIP 0 to 70oC, -40 to 85, CD74AC280E PACKAGE 14 Ld PDIP -55 to 125 Balanced Propagation Delays 0 to 70oC, -40 to 85,
-55 to 125 CD74AC280M AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply CD54ACT280F3A В±24mA Output Drive Current
-Fanout to 15 FASTв„ў ICs
-Drives 50Ω Transmission Lines -55 to 125 14 Ld CERDIP 0 to 70oC, -40 to 85, CD74ACT280E 14 Ld SOIC 14 Ld PDIP -55 to 125
0 to 70oC, -40 to 85,
-55 to 125 CD74ACT280M Description 14 Ld SOIC NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel. The ’AC280 and ’ACT280 are 9-bit odd/even parity generator/checkers that utilize Advanced CMOS Logic technology.
Both even and odd parity outputs are available for checking …