Datasheet Texas Instruments CDCEL949 — Даташит
| Производитель | Texas Instruments |
| Серия | CDCEL949 |
Программируемый синтезатор тактовых сигналов VCXO с 4 ФАПЧ и выходами LVCMOS 1,8 В
Datasheets
CDCE(L)913: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet
PDF, 1.5 Мб, Версия: F, Файл опубликован: 27 окт 2016
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Цены
 Купить CDCEL949 на РадиоЛоцман.Цены — от 136 до 16 377 ₽22 предложений от 17 поставщиков Тактовый синтезатор/устройство подавления колебаний Programmable 4-PLL VCXO Clock Synth | |||
| CDCEL949PWG4 Texas Instruments | от 136 ₽ | ||
| CDCEL949PWR Texas Instruments | 189 ₽ | ||
| CDCEL949PWR Texas Instruments | 254 ₽ | ||
| CDCEL949PWR Texas Instruments | от 599 ₽ | ||
Статус
| CDCEL949PW | CDCEL949PWG4 | CDCEL949PWR | CDCEL949PWRG4 | |
|---|---|---|---|---|
| Статус продукта | В производстве | В производстве | В производстве | В производстве |
| Доступность образцов у производителя | Да | Да | Да | Да |
Корпус / Упаковка / Маркировка
| CDCEL949PW | CDCEL949PWG4 | CDCEL949PWR | CDCEL949PWRG4 | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 24 | 24 | 24 | 24 |
| Package Type | PW | PW | PW | PW |
| Industry STD Term | TSSOP | TSSOP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 60 | 60 | 2000 | 2000 |
| Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R |
| Маркировка | CDCEL949 | CDCEL949 | CDCEL949 | CDCEL949 |
| Width (мм) | 4.4 | 4.4 | 4.4 | 4.4 |
| Length (мм) | 7.8 | 7.8 | 7.8 | 7.8 |
| Thickness (мм) | 1 | 1 | 1 | 1 |
| Pitch (мм) | .65 | .65 | .65 | .65 |
| Max Height (мм) | 1.2 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Скачать | Скачать | Скачать | Скачать |
Параметры
| Parameters / Models | CDCEL949PW | CDCEL949PWG4 | CDCEL949PWR | CDCEL949PWRG4 |
|---|---|---|---|---|
| Divider Ratio | Universal | Universal | Universal | Universal |
| Function | Clock Synthesizer | Clock Synthesizer | Clock Synthesizer | Clock Synthesizer |
| Input Level | Crystal, LVCMOS | Crystal, LVCMOS | Crystal, LVCMOS | Crystal, LVCMOS |
| Jitter-Peak to Peak(P-P) or Cycle to Cycle, C-C | 60 ps | 60 ps | 60 ps | 60 ps |
| Количество выходов | 9 | 9 | 9 | 9 |
| Рабочий диапазон температур, C | от -40 до 85 | от -40 до 85 | от -40 до 85 | от -40 до 85 |
| Output Frequency(Max), МГц | 230 | 230 | 230 | 230 |
| Output Level | LVCMOS | LVCMOS | LVCMOS | LVCMOS |
| Output Skew, ps | 150 | 150 | 150 | 150 |
| Package Group | TSSOP | TSSOP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) |
| Programmability | EEPROM | EEPROM | EEPROM | EEPROM |
| Rating | Catalog | Catalog | Catalog | Catalog |
| Special Features | Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC) | Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC) | Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC) | Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC) |
| VCC, В | 1.8 | 1.8 | 1.8 | 1.8 |
| VCC Core, В | 1.8 | 1.8 | 1.8 | 1.8 |
| VCC Out, В | 1.8 | 1.8 | 1.8 | 1.8 |
Экологический статус
| CDCEL949PW | CDCEL949PWG4 | CDCEL949PWR | CDCEL949PWRG4 | |
|---|---|---|---|---|
| RoHS | Совместим | Совместим | Совместим | Совместим |
Application Notes
- VCXO Application Guideline for CDCE(L)9xx Family (Rev. A)PDF, 107 Кб, Версия: A, Файл опубликован: 23 апр 2012
- Practical consideration on choosing a crystal for CDCE(L)9xx familyPDF, 60 Кб, Файл опубликован: 24 мар 2008
- Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913PDF, 297 Кб, Файл опубликован: 23 сен 2009
This document presents a method to smoothly change frequency by IВІCв„ў protocol on Texas Instruments CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 Clock Synthesizers, thus avoiding unnecessary intermediate frequencies. It also includes a code example to generate the IВІC protocol for the CDCE(L)9xx with the TMS320C645x. - Generating Low Phase-Noise Clocks for Audio Data Converters from Low FrequencyPDF, 860 Кб, Файл опубликован: 31 мар 2008
Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica - Troubleshooting I2C Bus ProtocolPDF, 184 Кб, Файл опубликован: 19 окт 2009
When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This
Модельный ряд
Серия: CDCEL949 (4)
Классификация производителя
- Semiconductors> Clock and Timing> Clock Generators> Spread-Spectrum Clocks
