Datasheet Texas Instruments DAC5681Z — Даташит
| Производитель | Texas Instruments |
| Серия | DAC5681Z |
16-битный интерполяционный цифро-аналоговый преобразователь (ЦАП) 1,0-GSPS 1x-4x
Datasheets
16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DAC. datasheet
PDF, 5.9 Мб, Версия: G, Файл опубликован: 3 дек 2015
Выписка из документа
Цены
Цифро-аналоговые преобразователи (ЦАП) 16B 1.0 GSPS 2x-4x Interpolating DAC | |||
| DAC5681Z | по запросу | ||
| DAC5681Z Texas Instruments | по запросу | ||
| DAC5681Z Texas Instruments | по запросу | ||
Статус
| DAC5681ZIRGCR | DAC5681ZIRGCT | |
|---|---|---|
| Статус продукта | В производстве | В производстве |
| Доступность образцов у производителя | Нет | Да |
Корпус / Упаковка / Маркировка
| DAC5681ZIRGCR | DAC5681ZIRGCT | |
|---|---|---|
| N | 1 | 2 |
| Pin | 64 | 64 |
| Package Type | RGC | RGC |
| Industry STD Term | VQFN | VQFN |
| JEDEC Code | S-PQFP-N | S-PQFP-N |
| Package QTY | 2000 | 250 |
| Carrier | LARGE T&R | SMALL T&R |
| Маркировка | DAC5681ZI | DAC5681ZI |
| Width (мм) | 9 | 9 |
| Length (мм) | 9 | 9 |
| Thickness (мм) | .88 | .88 |
| Pitch (мм) | .5 | .5 |
| Max Height (мм) | 1 | 1 |
| Mechanical Data | Скачать | Скачать |
Параметры
| Parameters / Models | DAC5681ZIRGCR | DAC5681ZIRGCT |
|---|---|---|
| Архитектура | Current Sink | Current Sink |
| DAC Channels | 1 | 1 |
| Interface | Parallel LVDS | Parallel LVDS |
| Interpolation | 1x,2x,4x | 1x,2x,4x |
| Рабочий диапазон температур, C | от -40 до 85 | от -40 до 85 |
| Package Group | VQFN | VQFN |
| Package Size: mm2:W x L, PKG | 64VQFN: 81 mm2: 9 x 9(VQFN) | 64VQFN: 81 mm2: 9 x 9(VQFN) |
| Power Consumption(Typ), mW | 800 | 800 |
| Rating | Catalog | Catalog |
| Разрешение, Bits | 16 | 16 |
| SFDR, дБ | 81 | 81 |
| Sample / Update Rate, MSPS | 1000 | 1000 |
Экологический статус
| DAC5681ZIRGCR | DAC5681ZIRGCT | |
|---|---|---|
| RoHS | Совместим | Совместим |
Application Notes
- Passive Terminations for Current Output DACsPDF, 244 Кб, Файл опубликован: 10 ноя 2008
The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance - High Speed Digital-to-Analog Converters Basics (Rev. A)PDF, 829 Кб, Версия: A, Файл опубликован: 23 окт 2012
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Мб, Файл опубликован: 2 июн 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Кб, Файл опубликован: 8 июн 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
Модельный ряд
Серия: DAC5681Z (2)
Классификация производителя
- Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)
