DS90LV110AT
www.ti.com SNOSAC2J – AUGUST 2004 – REVISED APRIL 2013 DS90LV110AT 1 to 10 LVDS Data/Clock Distributor with Failsafe
Check for Samples: DS90LV110AT FEATURES DESCRIPTION DS90LV110A is a 1 to 10 data/clock distributor
utilizing LVDS (Low Voltage Differential Signaling)
technology for low power, high speed operation. Data
paths are fully differential from input to output for low
noise generation and low pulse width distortion. The
design allows connection of 1 input to all 10 outputs.
LVDS I/O enable high speed data transmission for
point-to-point interconnects. This device can be used
as a high speed differential 1 to 10 signal distribution
/ fanout replacing multi-drop bus applications for
higher speed links with improved signal quality. It can
also be used for clock distribution up to 200MHz. 1 2 Low jitter 400 Mbps fully differential data path
145 ps (typ) of pk-pk jitter with PRBS = 223-1
data pattern at 400 Mbps
Single +3.3 V Supply
Balanced output impedance
Output channel-to-channel skew is 35ps (typ)
Differential output voltage (VOD) is 320mV (typ)
with 100О© termination load.
LVDS receiver inputs accept LVPECL signals
LVDS input failsafe …
