Datasheet ТI SN74F112NE4 — Даташит

SN74F112
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993 D OR N PACKAGE
(TOP VIEW) Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs 1CLK
1K
1J
1PRE
1Q
1Q
2Q
GND description
The SN74F112 contains two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the setup
time requirements is transferred to the outputs on
the negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not …