Datasheet Texas Instruments SN74GTL2014PWR — Даташит
| Производитель | Texas Instruments |
| Серия | SN74GTL2014 |
| Модель | SN74GTL2014PWR |
4-битный трансивер LVTTL-GTL 14-TSSOP от -40 до 85
Datasheets
SN74GTL2014 4-Channel LVTTL to GTL Transceiver datasheet
PDF, 885 Кб, Версия: A, Файл опубликован: 16 окт 2014
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Статус
| Статус продукта | В производстве (Рекомендуется для новых разработок) |
| Доступность образцов у производителя | Да |
Корпус / Упаковка / Маркировка
| Pin | 14 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Маркировка | GT14 |
| Width (мм) | 4.4 |
| Length (мм) | 5 |
| Thickness (мм) | 1 |
| Pitch (мм) | .65 |
| Max Height (мм) | 1.2 |
| Mechanical Data | Скачать |
Параметры
| Bits | 4 |
| F @ Nom Voltage(Max) | 150 Mhz |
| ICC @ Nom Voltage(Max) | 10 мА |
| Рабочий диапазон температур | от -40 до 85 C |
| Output Drive (IOL/IOH)(Max) | 50 мА |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 14TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | GTL |
| VCC(Max) | 3.6 В |
| VCC(Min) | 3 В |
| Voltage(Nom) | 3.3 В |
| tpd @ Nom Voltage(Max) | 7 нс |
Экологический статус
| RoHS | Совместим |
Application Notes
- GTLP in BTL ApplicationsPDF, 248 Кб, Файл опубликован: 31 июл 2000
- High-Performance Backplane Design With GTL+ (Rev. A)PDF, 135 Кб, Версия: A, Файл опубликован: 25 окт 1999
Results from a system that demonstrates the performance of GTL+ devices in a backplane are provided. The Texas Instruments (TI) GTL16622A is the example used in the design of the physical backplane. The TI backplane demonstration system is a useful tool for designers in understanding issues related to loading effects, termination, signal integrity, and data-transfer rate in a high-performance - Basic Design Considerations for Backplanes (Rev. B)PDF, 362 Кб, Версия: B, Файл опубликован: 5 апр 2001
This application report describes design issues relevant to the parallel backplanes typically used in the wireless, datacom, telecom, and networking markets. Designing a high-performance backplane is extremely complex, because issues such as distributed capacitance, stub lengths, noise margin, rise time (slew rate), flight time, and propagation delay must be defined and optimized to achieve good s - Logic in Live-Insertion Applications With a Focus on GTLPPDF, 493 Кб, Файл опубликован: 14 янв 2002
Live-insertion capability is an essential part of today?s high-speed data systems because those systems are expected to run continuously without being powered down. This application report delves into the cause and prevention of live-insertion and nanosecond-discontinuity effects, using both simulation and actual test measurements from a specially built GTLP EVM. Hypothetical cases for precharge c - Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)PDF, 585 Кб, Файл опубликован: 5 апр 2001
This application report compares two approaches for synchronous bus-system designs. The focus of the report is the comparison of a system using central-synchronous system clock (CSSC) with a system operated with a source-synchronous system clock (SSSC).The basic characteristics of lines, key factors that influence the bus line delay, and the impedance of bus lines are described.The theoretical - Fast GTLP Backplanes With the GTLPH1655 (Rev. A)PDF, 1.1 Мб, Версия: A, Файл опубликован: 19 сен 2000
This revision of the Fast GTL Backplanes With the GTL1655 application report addresses improvements, such as the improved OECE circuitry and implementation of theTexas Instruments TI-OPCE circuitry, that have been incorporated in the GTLPH1655 device. These improvements significantly improve signal integrity in distributed loads.This application report describes the physical principles of fast - GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A)PDF, 184 Кб, Версия: A, Файл опубликован: 1 мар 1997
GTL and BTL transceivers provide high-performance, excellent signal integrity and cost-effectiveness in high-speed backplane and point-to-point applications. This document discusses the GTL and BTL devices input/output (I/O) structure, power consumption, simultaneous switching, slew rate, and signal integrity. Design considerations for using these devices are provided. - Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)PDF, 390 Кб, Версия: B, Файл опубликован: 30 апр 2015
- Power-Up 3-State (PU3S) Circuits in TI Standard Logic DevicesPDF, 209 Кб, Файл опубликован: 10 май 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
Модельный ряд
Серия: SN74GTL2014 (1)
- SN74GTL2014PWR
Классификация производителя
- Semiconductors > Logic > Backplane Logic (GTL/TTL/BTL/ECL Transceiver/Translator)
