Datasheet Texas Instruments SN74LVT18512 — Даташит
| Производитель | Texas Instruments |
| Серия | SN74LVT18512 |
Устройства сканирования сканирования ABT 3,3 В с 18-битными универсальными шинными приемопередатчиками
Datasheets
3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers datasheet
PDF, 762 Кб, Файл опубликован: 1 окт 1997
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Цены
 Купить SN74LVT18512 на РадиоЛоцман.Цены — от 113 до 851 ₽23 предложений от 17 поставщиков Микросхема Логический чип, 3.3V ABT Scan Test Devices With 18Bit Universal Bus Transceivers 64-TSSOP -40℃ to 85℃ | |||
| SN74LVT18512DGGR Texas Instruments | 113 ₽ | ||
| SN74LVT18512DGGR Texas Instruments | от 194 ₽ | ||
| SN74LVT18512DGGR Texas Instruments | 270 ₽ | ||
| SN74LVT18512DGGR Texas Instruments | от 327 ₽ | ||
Статус
| SN74LVT18512DGGR | |
|---|---|
| Статус продукта | В производстве |
| Доступность образцов у производителя | Нет |
Корпус / Упаковка / Маркировка
| SN74LVT18512DGGR | |
|---|---|
| N | 1 |
| Pin | 64 |
| Package Type | DGG |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Маркировка | LVT18512 |
| Width (мм) | 6.1 |
| Length (мм) | 17 |
| Thickness (мм) | 1.15 |
| Pitch (мм) | .5 |
| Max Height (мм) | 1.2 |
| Mechanical Data | Скачать |
Параметры
| Parameters / Models | SN74LVT18512DGGR |
|---|---|
| Bits | 18 |
| F @ Nom Voltage(Max), Mhz | 160 |
| ICC @ Nom Voltage(Max), мА | 24 |
| Рабочий диапазон температур, C | от -40 до 85 |
| Output Drive (IOL/IOH)(Max), мА | 64/-32 |
| Package Group | TSSOP |
| Package Size: mm2:W x L, PKG | 64TSSOP: 138 mm2: 8.1 x 17(TSSOP) |
| Rating | Catalog |
| Technology Family | LVT |
| VCC(Max), В | 3.6 |
| VCC(Min), В | 2.7 |
| Voltage(Nom), В | 3.3 |
| tpd @ Nom Voltage(Max), нс | 4.9 |
Экологический статус
| SN74LVT18512DGGR | |
|---|---|
| RoHS | Совместим |
Application Notes
- Programming CPLDs Via the 'LVT8986 LASPPDF, 819 Кб, Файл опубликован: 1 ноя 2005
This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to - LVT Family Characteristics (Rev. A)PDF, 98 Кб, Версия: A, Файл опубликован: 1 мар 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Кб, Файл опубликован: 8 дек 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
Модельный ряд
Серия: SN74LVT18512 (1)
Классификация производителя
- Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic
