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Datasheet Texas Instruments SN74LVTH16373 — Даташит

ПроизводительTexas Instruments
СерияSN74LVTH16373
Datasheet Texas Instruments SN74LVTH16373

3,3 В ABT, 16-битные прозрачные защелки типа D с выходами с 3 состояниями

Datasheets

SN54LVTH16373, SN74LVTH16373 datasheet
PDF, 944 Кб, Версия: P, Файл опубликован: 1 ноя 2006
Выписка из документа

Цены

51 предложений от 28 поставщиков
Микросхема Логический замок, Latch Transparent 3-ST 16CH D-Type 48Pin TSSOP T/R Latch Transparent 3-ST 16CH D-Type 48Pin TSSOP T/R
ЭИК
Россия
SN74LVTH16373DLG4
Texas Instruments
от 118 ₽
Зенер
Россия и страны ТС
SN74LVTH16373DGG
от 217 ₽
Augswan
Весь мир
SN74LVTH16373ZRDR
Texas Instruments
по запросу
ТаймЧипс
Россия
SN74LVTH16373A
Texas Instruments
по запросу

Статус

74LVTH16373DGGRG474LVTH16373DLRG4SN74LVTH16373DGGRSN74LVTH16373DLSN74LVTH16373DLG4SN74LVTH16373DLRSN74LVTH16373ZQLRSN74LVTH16373ZRDR
Статус продуктаВ производствеВ производствеВ производствеВ производствеВ производствеВ производствеВ производствеВ производстве
Доступность образцов у производителяНетНетНетНетНетНетНетНет

Корпус / Упаковка / Маркировка

74LVTH16373DGGRG474LVTH16373DLRG4SN74LVTH16373DGGRSN74LVTH16373DLSN74LVTH16373DLG4SN74LVTH16373DLRSN74LVTH16373ZQLRSN74LVTH16373ZRDR
N12345678
Pin4848484848485654
Package TypeDGGDLDGGDLDLDLZQLZRD
Industry STD TermTSSOPSSOPTSSOPSSOPSSOPSSOPBGA MICROSTAR JUNIORBGA MICROSTAR JUNIOR
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PBGA-NR-PBGA-N
Package QTY2000100020002525100010001000
CarrierLARGE T&RLARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&RLARGE T&R
МаркировкаLVTH16373LVTH16373LVTH16373LVTH16373LVTH16373LVTH16373LL373LL373
Width (мм)6.17.496.17.497.497.494.55.5
Length (мм)12.515.8812.515.8815.8815.8878
Thickness (мм)1.152.591.152.592.592.59.75.8
Pitch (мм).5.635.5.635.635.635.65.8
Max Height (мм)1.22.791.22.792.792.7911.2
Mechanical DataСкачатьСкачатьСкачатьСкачатьСкачатьСкачатьСкачатьСкачать

Параметры

Parameters / Models74LVTH16373DGGRG4
74LVTH16373DGGRG4
74LVTH16373DLRG4
74LVTH16373DLRG4
SN74LVTH16373DGGR
SN74LVTH16373DGGR
SN74LVTH16373DL
SN74LVTH16373DL
SN74LVTH16373DLG4
SN74LVTH16373DLG4
SN74LVTH16373DLR
SN74LVTH16373DLR
SN74LVTH16373ZQLR
SN74LVTH16373ZQLR
SN74LVTH16373ZRDR
SN74LVTH16373ZRDR
3-State OutputYesYesYesYesYesYesYesYes
Bits1616161616161616
F @ Nom Voltage(Max), Mhz160160160160160160160160
ICC @ Nom Voltage(Max), мА55555555
Рабочий диапазон температур, Cот -40 до 85от -40 до 85от -40 до 85от -40 до 85от -40 до 85от -40 до 85от -40 до 85от -40 до 85
Output Drive (IOL/IOH)(Max), мА64/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-32
Package GroupTSSOPSSOPTSSOPSSOPSSOPSSOPBGA MICROSTAR JUNIORBGA MICROSTAR JUNIOR
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), В3.63.63.63.63.63.63.63.6
VCC(Min), В2.72.72.72.72.72.72.72.7
Voltage(Nom), В3.33.33.33.33.33.33.33.3
tpd @ Nom Voltage(Max), нс3.83.83.83.83.83.83.83.8

Экологический статус

74LVTH16373DGGRG474LVTH16373DLRG4SN74LVTH16373DGGRSN74LVTH16373DLSN74LVTH16373DLG4SN74LVTH16373DLRSN74LVTH16373ZQLRSN74LVTH16373ZRDR
RoHSСовместимСовместимСовместимСовместимСовместимСовместимСовместимСовместим

Application Notes

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Кб, Версия: A, Файл опубликован: 1 мар 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Кб, Файл опубликован: 8 дек 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Кб, Файл опубликован: 5 фев 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Кб, Версия: B, Файл опубликован: 22 май 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Кб, Версия: A, Файл опубликован: 1 авг 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Кб, Файл опубликован: 1 май 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Кб, Файл опубликован: 10 май 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
  • Live Insertion
    PDF, 150 Кб, Файл опубликован: 1 окт 1996
    Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance and repair. To avoid damaging components additional circuitry modifications are necessary. This document describes in detail the phenomena tha
  • Input and Output Characteristics of Digital Integrated Circuits
    PDF, 1.7 Мб, Файл опубликован: 1 окт 1996
    This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Кб, Версия: A, Файл опубликован: 6 фев 2015

Модельный ряд

Классификация производителя

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Latch

На английском языке: Datasheet Texas Instruments SN74LVTH16373

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