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Datasheet Texas Instruments CLVTH16373IDGGREP — Даташит

ПроизводительTexas Instruments
СерияSN74LVTH16373-EP
МодельCLVTH16373IDGGREP
Datasheet Texas Instruments CLVTH16373IDGGREP

Усовершенствованный продукт 3,3 В, около 16 бит, прозрачные защелки типа D с выходами с 3 состояниями 48-TSSOP от -40 до 85

Datasheets

SN74LVTH16373-EP 3.3-V ABT 16-Bit Transparent D-Type Latch With Tri-State Outputs datasheet
PDF, 945 Кб, Версия: B, Файл опубликован: 29 июн 2016
Выписка из документа

Цены

16 предложений от 14 поставщиков
Микросхема Логический замок, Enhanced Product 3.3V Abt 16Bit Transparent D-Type Latches With 3-State Outputs 48-TSSOP -40℃ to 85℃
EIS Components
Весь мир
CLVTH16373IDGGREP
Texas Instruments
65 ₽
ChipWorker
Весь мир
CLVTH16373IDGGREP
Texas Instruments
399 ₽
Кремний
Россия и страны СНГ
CLVTH16373IDGGREP
Texas Instruments
по запросу
CLVTH16373IDGGREP
Texas Instruments
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Статус

Статус продуктаВ производстве (Рекомендуется для новых разработок)
Доступность образцов у производителяНет

Корпус / Упаковка / Маркировка

Pin48
Package TypeDGG
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
МаркировкаLH16373EP
Width (мм)6.1
Length (мм)12.5
Thickness (мм)1.15
Pitch (мм).5
Max Height (мм)1.2
Mechanical DataСкачать

Параметры

3-State OutputYes
Bits16
F @ Nom Voltage(Max)160 Mhz
ICC @ Nom Voltage(Max)5 мА
Тип входаTTL
Рабочий диапазон температурот -40 до 85,-55 до 125 C
Output Drive (IOL/IOH)(Max)64/-32 мА
Тип выходаTTL
Package GroupTSSOP
Package Size: mm2:W x L48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG
RatingHiRel Enhanced Product
Technology FamilyLVT
VCC(Max)3.6 В
VCC(Min)2.7 В
tpd @ Nom Voltage(Max)3.8 нс

Экологический статус

RoHSСовместим

Application Notes

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Кб, Версия: A, Файл опубликован: 1 мар 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Кб, Файл опубликован: 8 дек 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Кб, Версия: B, Файл опубликован: 22 май 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Кб, Версия: A, Файл опубликован: 1 авг 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Кб, Файл опубликован: 1 май 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Кб, Файл опубликован: 10 май 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Кб, Версия: A, Файл опубликован: 6 фев 2015

Модельный ряд

Классификация производителя

  • Semiconductors > Space & High Reliability > Logic Products > Flip-Flop/Latch/Registers

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