Datasheet Texas Instruments SN74LVTH18512DGGR — Даташит
| Производитель | Texas Instruments |
| Серия | SN74LVTH18512 |
| Модель | SN74LVTH18512DGGR |
Устройства сканирования ABT 3,3 В с 18-битными приемопередатчиками универсальной шины 64-TSSOP от -40 до 85
Datasheets
3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers datasheet
PDF, 735 Кб, Версия: B, Файл опубликован: 1 окт 1997
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Цены
 Купить SN74LVTH18512DGGR на РадиоЛоцман.Цены — от 124 до 1 372 ₽29 предложений от 15 поставщиков Микросхема Логический контроллер, 3.3V ABT Scan Test Devices With 18Bit Universal Bus Transceivers 64-TSSOP -40℃ to 85℃ | |||
| SN74LVTH18512DGGR Texas Instruments | 267 ₽ | ||
| SN74LVTH18512DGGR Texas Instruments | от 359 ₽ | ||
| SN74LVTH18512DGGR Kingbright | по запросу | ||
| SN74LVTH18512DGGR Texas Instruments | по запросу | ||
Статус
| Статус продукта | В производстве (Рекомендуется для новых разработок) |
| Доступность образцов у производителя | Нет |
Корпус / Упаковка / Маркировка
| Pin | 64 |
| Package Type | DGG |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Маркировка | LVTH18512 |
| Width (мм) | 6.1 |
| Length (мм) | 17 |
| Thickness (мм) | 1.15 |
| Pitch (мм) | .5 |
| Max Height (мм) | 1.2 |
| Mechanical Data | Скачать |
Параметры
| Bits | 18 |
| F @ Nom Voltage(Max) | 160 Mhz |
| ICC @ Nom Voltage(Max) | 24 мА |
| Рабочий диапазон температур | от -40 до 85 C |
| Output Drive (IOL/IOH)(Max) | 64/-32 мА |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 64TSSOP: 138 mm2: 8.1 x 17(TSSOP) PKG |
| Rating | Catalog |
| Technology Family | LVT |
| VCC(Max) | 3.6 В |
| VCC(Min) | 2.7 В |
| Voltage(Nom) | 3.3 В |
| tpd @ Nom Voltage(Max) | 4.9 нс |
Экологический статус
| RoHS | Совместим |
Application Notes
- Programming CPLDs Via the 'LVT8986 LASPPDF, 819 Кб, Файл опубликован: 1 ноя 2005
This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to - LVT Family Characteristics (Rev. A)PDF, 98 Кб, Версия: A, Файл опубликован: 1 мар 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Кб, Файл опубликован: 8 дек 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed. - Bus-Hold CircuitPDF, 418 Кб, Файл опубликован: 5 фев 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
Модельный ряд
Серия: SN74LVTH18512 (2)
- 74LVTH18512DGGRE4 SN74LVTH18512DGGR
Классификация производителя
- Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic
