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Datasheet Texas Instruments SN74LVTH373 — Даташит

ПроизводительTexas Instruments
СерияSN74LVTH373
Datasheet Texas Instruments SN74LVTH373

Восьмеричные прозрачные защелки ABT типа D, 3,3 В, с выходами с 3 состояниями

Datasheets

SN54LVTH373, SN74LVTH373 datasheet
PDF, 1.3 Мб, Версия: H, Файл опубликован: 13 окт 2003
Выписка из документа

Цены

36 предложений от 25 поставщиков
Микросхема Логический замок, Latch Transparent 3-ST 8CH D-Type 20Pin SOIC T/R
AiPCBA
Весь мир
SN74LVTH373ANSRG4
Texas Instruments
21 ₽
ЧипСити
Россия
SN74LVTH373DW
Texas Instruments
26 ₽
LifeElectronics
Россия
SN74LVTH373
Texas Instruments
по запросу
Augswan
Весь мир
SN74LVTH373PWRG4
Texas Instruments
по запросу

Статус

SN74LVTH373DBRSN74LVTH373DWSN74LVTH373DWG4SN74LVTH373DWRSN74LVTH373DWRG4SN74LVTH373NSRSN74LVTH373PWSN74LVTH373PWG4SN74LVTH373PWRSN74LVTH373PWRE4SN74LVTH373PWRG4
Статус продуктаВ производствеВ производствеВ производствеВ производствеВ производствеВ производствеВ производствеВ производствеВ производствеВ производствеВ производстве
Доступность образцов у производителяНетНетНетНетНетНетНетНетНетНетНет

Корпус / Упаковка / Маркировка

SN74LVTH373DBRSN74LVTH373DWSN74LVTH373DWG4SN74LVTH373DWRSN74LVTH373DWRG4SN74LVTH373NSRSN74LVTH373PWSN74LVTH373PWG4SN74LVTH373PWRSN74LVTH373PWRE4SN74LVTH373PWRG4
N1234567891011
Pin2020202020202020202020
Package TypeDBDWDWDWDWNSPWPWPWPWPW
Industry STD TermSSOPSOICSOICSOICSOICSOPTSSOPTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY200025252000200020007070200020002000
CarrierLARGE T&RTUBETUBELARGE T&RLARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&RLARGE T&R
МаркировкаLXH373LVTH373LVTH373LVTH373LVTH373LVTH373LXH373LXH373LXH373LXH373LXH373
Width (мм)5.37.57.57.57.55.34.44.44.44.44.4
Length (мм)7.212.812.812.812.812.66.56.56.56.56.5
Thickness (мм)1.952.352.352.352.351.9511111
Pitch (мм).651.271.271.271.271.27.65.65.65.65.65
Max Height (мм)22.652.652.652.6521.21.21.21.21.2
Mechanical DataСкачатьСкачатьСкачатьСкачатьСкачатьСкачатьСкачатьСкачатьСкачатьСкачатьСкачать

Параметры

Parameters / ModelsSN74LVTH373DBR
SN74LVTH373DBR
SN74LVTH373DW
SN74LVTH373DW
SN74LVTH373DWG4
SN74LVTH373DWG4
SN74LVTH373DWR
SN74LVTH373DWR
SN74LVTH373DWRG4
SN74LVTH373DWRG4
SN74LVTH373NSR
SN74LVTH373NSR
SN74LVTH373PW
SN74LVTH373PW
SN74LVTH373PWG4
SN74LVTH373PWG4
SN74LVTH373PWR
SN74LVTH373PWR
SN74LVTH373PWRE4
SN74LVTH373PWRE4
SN74LVTH373PWRG4
SN74LVTH373PWRG4
3-State OutputYesYesYesYesYesYesYesYesYesYesYes
Bits88888888888
F @ Nom Voltage(Max), Mhz160160160160160160160160160160160
ICC @ Nom Voltage(Max), мА55555555555
Рабочий диапазон температур, Cот -40 до 85от -40 до 85от -40 до 85от -40 до 85от -40 до 85от -40 до 85от -40 до 85от -40 до 85от -40 до 85от -40 до 85от -40 до 85
Output Drive (IOL/IOH)(Max), мА64/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-32
Package GroupSSOPSOICSOICSOICSOICSOTSSOPTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SO: 98 mm2: 7.8 x 12.6(SO)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), В3.63.63.63.63.63.63.63.63.63.63.6
VCC(Min), В2.72.72.72.72.72.72.72.72.72.72.7
Voltage(Nom), В3.33.33.33.33.33.33.33.33.33.33.3
tpd @ Nom Voltage(Max), нс3.93.93.93.93.93.93.93.93.93.93.9

Экологический статус

SN74LVTH373DBRSN74LVTH373DWSN74LVTH373DWG4SN74LVTH373DWRSN74LVTH373DWRG4SN74LVTH373NSRSN74LVTH373PWSN74LVTH373PWG4SN74LVTH373PWRSN74LVTH373PWRE4SN74LVTH373PWRG4
RoHSСовместимСовместимСовместимСовместимСовместимСовместимСовместимСовместимСовместимСовместимСовместим

Application Notes

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Кб, Версия: A, Файл опубликован: 1 мар 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Кб, Файл опубликован: 8 дек 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Кб, Файл опубликован: 5 фев 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Модельный ряд

Классификация производителя

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Latch

На английском языке: Datasheet Texas Instruments SN74LVTH373

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