Datasheet Linear Technology LTC3025EDC-1#TRMPBF — Даташит

Datasheets

Цены

Купить LTC3025EDC-1#TRMPBF на РадиоЛоцман.Цены — от 81 до 497 ₽ 26 предложений от 14 поставщиков Чип стабилизации напряжения, LDO Regulator Pos 0.4V to 3.6V 0.5A 6Pin DFN EP T/R
Lixinc Electronics Весь мир	LTC3025EDC-1#TRMPBF Linear Technology	от 153 ₽	Купить
ЭИК Россия	LTC3025EDC-1#TRMPBF Analog Devices	от 458 ₽	Купить
Augswan Весь мир	LTC3025EDC-1#TRMPBF Analog Devices	по запросу	Купить
Кремний Россия и страны СНГ	LTC3025EDC-1#TRMPBF	по запросу	Купить

Корпус / Упаковка / Маркировка

Параметры

Экологический статус

Другие варианты исполнения

LTC3025-2 LTC3025-2 LTC3025-3 LTC3025-3 LTC3025-4 LTC3025-4

Design Notes

• Скачать
  Powering Altera Arria 10 FPGA and Arria 10 SoC: Tested and Verified Power Management Solutions &mdash DN549
  PDF, 1.6 Мб, Файл опубликован: 19 фев 2016
  Выписка из документа

  Powering Altera ArriaВ 10 FPGA andВ Arria 10 SoC: Tested
  and Verified Power Management Solutions
  Design Note 549
  Afshin Odabaee
  Introduction
  FPGA development kits allow system developers to
  evaluate an FPGA without having to design a complete
  system. Figures 1 and 2 show Altera’s new 20nm
  Arria 10 FPGAs and Arria 10В SoCs (System-on-Chip)
  development boards. These boards are tested and
  verified by Altera, exemplifying best design practices
  in layout, signal integrity and power management.
  Power Management for Core, System and I/O
  The power management solution for high end FPGAs,
  including the Arria 10, should be carefully selected.
  A well thought-out power management design can
  reduce PCB size, weight and complexity, as well as
  lower power consumption and cooling costs. And it
  is essential to achieve optimal system performance.
  ForВ example, the 0.95V at 105A supplied by the 12V
  DC/DC regulator powering the core of the Arria 10 GX
  FPGA in Figure 1 has several features that complement
  the power saving schemes of the SoC: Figure 1. Arria 10 GX FPGA Development Kit …

Статьи

• Скачать
  Avoid Debugging Cycles in Power Management for FPGA, GPU and ASIC Systems &mdash LT Journal
  PDF, 3.2 Мб, Файл опубликован: 25 авг 2016
  Выписка из документа

  Avoid Debugging Cycles in Power Management for FPGA,
  GPU and ASIC Systems
  Afshin Odabaee When it comes to designing FPGA, GPU or ASIC controlled systems, the number of
  design challenges related to power management and analog systems pale in comparison
  to those related to digital design. Nevertheless, it is risky to assume that power system
  design can be left to “later,” or taken in line with digital design. Even seemingly innocuous
  problems in power supply design can significantly delay the release of a system, as any
  added time to the power system debugging cycle can halt all work on the digital side.
  A good way to put DC/DC regulation
  issues to rest is to use a verified development kit offered by the FPGA, GPU or
  ASIC vendor. Often, the design itself or
  a similar design is available as a board/
  kit by the suppliers of power products
  and FPGA, GPU and ASIC manufacturers. Using a tested and verified kit unburdens
  system designers of most power system
  and analog issues, allowing them instead
  to focus their energies on configuring the
  complex digital systems. The optimum
  power system layout is taken care of
  before significant design is undertaken. THOUGHTFUL POWER MANAGEMENT
  IS CHALLENGING AT THE START Every design task is initially daunting,
  and power management design is no
  exception. This is the case when power is …

Модельный ряд

Классификация производителя

• Power Management > LDO Linear Regulators > Positive Linear Regulators (LDO)

Варианты написания:

LTC3025EDC-1TRMPBF, LTC3025EDC-1 TRMPBF, LTC3025EDC1#TRMPBF, LTC3025EDC 1#TRMPBF