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Купить LTC2977 на РадиоЛоцман.Цены — от 230 до 3 226 ₽ 31 предложений от 20 поставщиков LINEAR TECHNOLOGY LTC2977IUP#TRPBF Special Function IC, 8Channel Power System Manager, 4.5V to 15V, QFN-64
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Application Notes

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  Accurate Temperature Sensing with an External P-N Junction &mdash AN137
  PDF, 540 Кб, Файл опубликован: 20 сен 2012
  Many Linear Technology devices use an external PNP transistor to sense temperature. Common examples are LTC3880, LTC3883 and LTC2974. Accurate temperature sensing depends on proper PNP selection, layout, and device configuration. This application note reviews the theory of temperature sensing and gives practical advice on implementation.
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  Application Note 137
  May 2012
  Accurate Temperature Sensing with an External P-N
  Junction
  Michael Jones
  Introduction Temperature Sensing Theory Many Linear Technology devices use an external PNP
  transistor to sense temperature. Common examples are
  LTC3880, LTC3883 and LTC2974. Accurate temperature
  sensing depends on proper PNP selection, layout, and
  device configuration. This application note reviews the
  theory of temperature sensing and gives practical advice
  on implementation. Linear Technology devices use an external bipolar transistor p-n junction to measure temperature. The relationship
  between forward voltage, current, and temperature is: Why should you worry about implementing temperature
  sensing? Can’t you just put the sensor near your inductor
  and lay out your circuit any way you want? Unfortunately,
  poor routing can sacrifice temperature measurement
  performance and compensation. The purpose of this application note is to allow you the opportunity to get it right
  the first time, so you don’t have to change the layout after
  your board is fabricated.
  Why Use Temperature Sensing?
  Some Linear Technology devices measure internal and
  external temperature. Internal temperature is used to
  protect the device by shutting down operation or locking …

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  Overview of the EEPROM in LTC PSM Devices &mdash AN145
  PDF, 3.0 Мб, Файл опубликован: 10 май 2014
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  Application Note 145
  July 2015
  Overview of the EEPROM in LTC PSM Devices
  Nick Vergunst Introduction convenient List Of All Options Linear TechnologyВ® has a large family of devices that
  provide a great deal of power and configurability for all
  applications. These parts additionally provide onboard
  nonvolatile memory (NVM) in the form of EEPROM to
  store and recall configuration parameters and on some
  devices provide a fault log and user scratch pad. Option 1A. Manual programming with LTpowerPlayв„ў
  Built In Programming Utility (PC->NVM) These Power System Management(PSM) devices’ architectures allow them to power up and load the desired
  configuration parameters from this NVM autonomously
  with no I2C or firmware interaction required.
  A common question customers ask is, “Now that I have
  settled on a particular configuration, how do I program
  this configuration into the chip’s onboard nonvolatile
  memory (NVM).”
  Some available options are presented in rough order of
  increasing complexity throughout the document.
  NOTE: Linear Technology strongly recommends
  Option 1 for preproduction prototyping, and
  OptionВ 2, Option 3 or Option 4 for higher volume
  production. Option 5 is a convenient method to
  program a small quantity of loose ICs prior to board …

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  Power System Management Addressing &mdash AN152
  PDF, 169 Кб, Файл опубликован: 12 июл 2016
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  Application Note 152
  July 2016
  Power System Management Addressing
  Michael Jones Introduction
  The foundation of all PMBus applications, including LTCВ®
  Power System Management (PSM), is the ability for the
  PMBus master (system host) to communicate with all
  PMBus slaves (PSM controllers, PSM managers, PSM
  ВµModulesВ®, and PMBus monolithic devices) on the bus.
  Every slave on the bus must have a unique address that
  does not conflict with other devices.
  The bus master must also be able to communicate with
  PSM slaves in a few less than obvious situations: Address discovery Global actions Multiphase rails Invalid NVM Bus MUXes
  Device addressing is achieved with a combination of base
  registers plus external address select (ASEL) pins, as well
  as special global, rail, ARA, and other special addresses.
  This Application Note will present the fundamental design
  principles underlying the LTC PSM family, details on product
  family differences, as well practical examples and advice.
  Special cases, such as invalid NVM, will also be discussed.
  The benefit to you is a design that works on day one, and
  works even when things go wrong. For example, if you
  are writing to the NVM with LTpowerPlayв„ў, and power is …

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  Linduino for Power System Management &mdash AN153
  PDF, 1.3 Мб, Файл опубликован: 24 фев 2016
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  Application Note 153
  July 2016
  Linduino for Power System Management
  Michael Jones
  INTRODUCTION LTC3880, and the industry standards for I2C/SMBus/
  PMBus. Most Power System Management designs follow a set
  and forget model. Setup and debug of Power System
  Management (PSM) devices is simple with LTpowerPlayВ®
  and when combined with a bulk programing solution, there
  is no need for firmware. However, many large systems
  require a Board Management Controller (BMC), begging
  the question: “What can firmware do for PSM?” Linduino PSM hardware consists of a Linduino (DC2026),
  and a shield to connect (DC2294) the I2C pins of the
  Linduino to an PMBus/SMBus/I2C Bus of a demo board
  or product board. The foundation of PSM firmware is PMBus; the foundation
  of PMBus is SMBus; and the foundation of SMBus is I2C.
  Building a BMC that adds value with PSM firmware requires
  some level of knowledge of each protocol, or a pre-existing
  library that frees the programmer from the details. For optimal learning, start with a DC2026 (Linduino),
  DC2294 (Shield), DC1962 (Power Stick), and a Total
  Phase Beagle (I2C Sniffer). This allows programming,
  debugging, and learning of controllers (LTC388X) and
  managers (LTC297X). The LinduinoВ® libraries handle each protocol layer, and …

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  Fault Log Decoding with Linduino PSM &mdash AN155
  PDF, 230 Кб, Файл опубликован: 26 янв 2017
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  Application Note 155
  January 2017
  Fault Log Decoding with Linduino PSM
  Michael Jones Introduction
  LTC power system management devices are PMBus controlled point-of-load converters (LTCВ®388X) and power
  system managers (LTC297X). All LTC power system management (PSM) devices have a fault log that is written
  to EEPROM when there is a fault. Once the fault log is
  written, fault logs are no longer generated until they are
  re-enabled, typically after the data has been read back.
  LTpowerPlayВ® helps debug a system by reading the fault
  log, decoding it into human-readable format, displaying it
  and saving it to a file. A system with a board management
  controller (BMC), can also read the fault log from EEPROM
  and re-enable it. Firmware can store, transfer over a
  network and decode fault data read from a PSM device.
  The LinduinoВ® Sketchbook contains an example sketch
  that reads fault logs, along with the supporting libraries
  for PMBus and fault log decoding.
  This application note describes the basics of reading and
  decoding fault logs using Linduino.
  Hardware
  The hardware used for this application note is:
  1. DC2026 (Linduino) …

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  In Flight Update with Linduino &mdash AN166
  PDF, 1.1 Мб, Файл опубликован: 10 апр 2017
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  Application Note 166
  April 2017
  In Flight Update with Linduino
  Michael Jones
  INTRODUCTION TO INFLIGHT UPDATE INFLIGHT UPDATE PROCESS Inflight Update is a method of modifying the stored settings of LTC Power System Management (PSM) devices,
  including application of the new settings, to a live system1 . The general dataflow of Infight Update is a simple linear
  progression: Inflight Update is a two-stage process: EEPROM is modified
  first, and then EEPROM is copied to RAM. During stage
  one, a Board Management Controller sends new settings
  directly to the EEPROM via PMBus while the devices are
  operating normally, without impacting operation. During
  stage two, all devices switch to the new configuration via
  a reset or a power cycle2 .
  Decoupling “programming settings” from “application of
  settings” allows the EEPROM programming mechanism
  to stage, validate, and recover from programming failure
  without interruption of delivered power. This minimizes
  system downtime because all rails are power cycled only
  once per update.
  Inflight Update solves several technical and business
  problems. Fast product development increases the probability of field problems. For example, the supervisors
  might require more margin to reduce false positives.
  An FPGA image update might require small changes to …

Design Notes

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  Powering Altera Arria 10 FPGA and Arria 10 SoC: Tested and Verified Power Management Solutions &mdash DN549
  PDF, 1.6 Мб, Файл опубликован: 19 фев 2016
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  Powering Altera ArriaВ 10 FPGA andВ Arria 10 SoC: Tested
  and Verified Power Management Solutions
  Design Note 549
  Afshin Odabaee
  Introduction
  FPGA development kits allow system developers to
  evaluate an FPGA without having to design a complete
  system. Figures 1 and 2 show Altera’s new 20nm
  Arria 10 FPGAs and Arria 10В SoCs (System-on-Chip)
  development boards. These boards are tested and
  verified by Altera, exemplifying best design practices
  in layout, signal integrity and power management.
  Power Management for Core, System and I/O
  The power management solution for high end FPGAs,
  including the Arria 10, should be carefully selected.
  A well thought-out power management design can
  reduce PCB size, weight and complexity, as well as
  lower power consumption and cooling costs. And it
  is essential to achieve optimal system performance.
  ForВ example, the 0.95V at 105A supplied by the 12V
  DC/DC regulator powering the core of the Arria 10 GX
  FPGA in Figure 1 has several features that complement
  the power saving schemes of the SoC: Figure 1. Arria 10 GX FPGA Development Kit …

Статьи

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  Avoid Debugging Cycles in Power Management for FPGA, GPU and ASIC Systems &mdash LT Journal
  PDF, 3.2 Мб, Файл опубликован: 25 авг 2016
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  Avoid Debugging Cycles in Power Management for FPGA,
  GPU and ASIC Systems
  Afshin Odabaee When it comes to designing FPGA, GPU or ASIC controlled systems, the number of
  design challenges related to power management and analog systems pale in comparison
  to those related to digital design. Nevertheless, it is risky to assume that power system
  design can be left to “later,” or taken in line with digital design. Even seemingly innocuous
  problems in power supply design can significantly delay the release of a system, as any
  added time to the power system debugging cycle can halt all work on the digital side.
  A good way to put DC/DC regulation
  issues to rest is to use a verified development kit offered by the FPGA, GPU or
  ASIC vendor. Often, the design itself or
  a similar design is available as a board/
  kit by the suppliers of power products
  and FPGA, GPU and ASIC manufacturers. Using a tested and verified kit unburdens
  system designers of most power system
  and analog issues, allowing them instead
  to focus their energies on configuring the
  complex digital systems. The optimum
  power system layout is taken care of
  before significant design is undertaken. THOUGHTFUL POWER MANAGEMENT
  IS CHALLENGING AT THE START Every design task is initially daunting,
  and power management design is no
  exception. This is the case when power is …

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• Monitor, Control and Protection > Digital Power System Management > Digital Power System Managers