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CAB4A
www.ti.com SNAS630B – JULY 2013 – REVISED OCTOBER 2013 CAB4A -DDR4 Register
32-Bit 1:2 Command/Address/Control Buffer and 1:4 Differential Clock Buffer
Check for Samples: CAB4A FEATURES DESCRIPTION The CAB4 is 32-bit 1:2 Command/Address/Control
Buffer and 1:4 differential Clock Buffer designed for
operation on DDR4 registered DIMMs with a 1.2 V
VDD mode. 1 23 DDR4RCD01 JEDEC Compliant
DDR4 RDIMM and LRDIMM up to DDR4-2400
32 Bits 1-to-2 Register Outputs
1-to-4 Differential Clock Buffer
1.2V Operation
PLL with Internal Feedback
Configurable Driver Strength
Scalable Weak Driver
Programmable Latency
Output Driver Calibration
Address Mirroring and Inversion
DDR4 Full-Parity Operation
On-Chip Programmable VREF Generation
CA Bus Training Mode
I2Cв„ў Interface Support
Up to 16-Logical Ranks Support for 3DS
RDIMMs and LRDIMMs …
