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Экологический статус

Application Notes

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  Multi-Part Clock Synchronization Methods for Large Data Acquisition Systems &mdash AN165
  PDF, 1.2 Мб, Файл опубликован: 4 апр 2017
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  Application Note 165
  September 2017
  Multi-Part Clock Synchronization Methods for Large
  Data Acquisition Systems
  Doug La Porte
  Introduction
  High speed data conversion systems requiring a large
  number of low jitter clock signals often need to use multiple clocking devices. Compared to a clocking architecture
  requiring only a single clocking device, an architecture
  utilizing multiple devices complicates the system design
  in two major respects. First, these multiple devices must
  be synchronized to assure consistent clock phasing at all
  outputs. Second, maintaining low jitter is difficult as every
  device in the clocking system adds more noise. Designing
  a synchronized clocking system with both low jitter and a
  large number of outputs is a challenge.
  Fortunately, Linear Technology’s family of frequency
  synthesizers and clock distribution products addresses
  these concerns. For the purpose of this application note,
  it is convenient to sort all parts in the product family into
  PLL WITH DIVIDERS
  AND DISTRIBUTION
  (PLL+DIST) REFERENCE …

Статьи

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  1.4GHz Low Jitter PLL with Clock Distribution Solves Difficult Clocking Problems: Multi-Clock Synchronization and Data Converter Clocking &mdash LT Journal
  PDF, 732 Кб, Файл опубликован: 22 янв 2015
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  design features 1.4GHz Low Jitter PLL with Clock Distribution Solves Difficult
  Clocking Problems: Multi-Clock Synchronization and Data
  Converter Clocking
  Chris Pearson Two of the more difficult challenges facing clock system designers are synchronizing
  multiple system clocks and creating low jitter data converter clocks. The LTC6950
  overcomes these challenges by featuring Linear Technology’s easy-to-use EZSync™
  technology and providing five clock outputs with less than 100fs RMS additive jitter.
  Other multi-clock synchronization solutions involve aligning the edges of two or
  more high speed input signals within an
  extremely precise time window, sometimes within a couple nanoseconds. Such
  devices, hinting at the unreliability of this
  synchronization method, often include a
  SYNCRESULT pin to indicate whether the
  synchronization passed or failed, requiring a retry. The elegance of EZSync is it
  eliminates the need for precision alignment of any high speed input signals,
  while assuring consistent edge alignment
  of all outputs on one or multiple EZSync
  clock devices. With EZSync, synchronizing multiple devices, multiple boards
  and even multiple system level clock
  edges is as easy as pressing a button.
  The LTC6950 produces five low jitter,
  high slew rate differential clocks. These
  clock characteristics allow designers to clock multiple high speed data …

Модельный ряд

Классификация производителя

• Timing > Clock Generation and Distribution > Clock Generation | Clock Distribution
• Timing > PLL Synthesizers & VCOs > Integer-N PLLs

Варианты написания:

LTC6950IUHHPBF, LTC6950IUHH PBF