Datasheet Intersil HSP50214BVI — Даташит

HSP50214B В® Data Sheet May 1, 2007 FN4450.4 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts
digitized IF data into filtered baseband data which can be
processed by a standard DSP microprocessor. The
Programmable Downconverter (PDC) performs down
conversion, decimation, narrowband low pass filtering, gain
scaling, resampling, and Cartesian to Polar coordinate
conversion. Up to 65MSPS Front-End Processing Rates (CLKIN) and
55MHz Back-End Processing Rates (PROCCLK)
Clocks May Be Asynchronous The 14-bit sampled IF input is down converted to baseband
by digital mixers and a quadrature NCO, as shown in the
Block Diagram. A decimating (4 to 32) fifth order Cascaded
Integrator-Comb (CIC) filter can be applied to the data
before it is processed by up to 5 decimate-by-2 halfband
filters. The halfband filters are followed by a 255-tap
programmable FIR filter. The output data from the
programmable FIR filter is scaled by a digital AGC before
being re-sampled in a polyphase FIR filter. The output
section can provide seven types of data: Cartesian (I, Q),
polar (R, Оё), filtered frequency (dОё/dt), Timing Error (TE), and
AGC level in either parallel or serial format. Processing Capable of >100dB SFDR Up to 255-Tap Programmable FIR Overall Decimation Factor Ranging from 4 to 16384 Output Samples Rates to в‰… 12.94MSPS with Output
Bandwidths to в‰… 982kHz Lowpass 32-Bit Programmable NCO for Channel Selection and
Carrier Tracking Digital Resampling Filter for Symbol Tracking Loops and
Incommensurate Sample-to-Output Clock Ratios Digital AGC with Programmable Limits and Slew Rate to …