Datasheet Intersil HD-6402-883 — Даташит

DATASHEET
HD-6402/883 FN2953
Rev 1.00
March 1997 CMOS Universal AsynchronousReceiver Transmitter (UART) Features Description This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1. The HD-6402/883 is a CMOS UART for interfacing computers or microprocessors to an asynchronous serial data channel. The receiver converts serial start, data, parity and stop
bits. The transmitter converts parallel data into serial form
and automatically adds start, parity and stop bits. The data
word length can be 5, 6, 7 or 8 bits. Parity may be odd or
even. Parity checking and generation can be inhibited. The
stop bits may be one or two or one and one-half when transmitting 5-bit code. 8.0MHz Operating Frequency (HD-6402/883B) 2.0MHz Operating Frequency (HD-6402/883R) Low Power CMOS Design Programmable Word Length, Stop Bits and Parity Automatic Data Formatting and Status Generation Compatible with Industry Standard UARTs Single +5V Power Supply CMOS/TTL Compatible Inputs The HD-6402/883 can be used in a wide range of applications including modems, printers, peripherals and remote
data acquisition systems. Utilizing the Intersil advanced
scaled SAJI IV CMOS process permits operation clock frequencies up to 8.0MHz (500K Baud). Power requirements,
by comparison, are reduced from 300mW to 10mW. Status
logic increases flexibility and simplifies the user interface. Ordering Information
PACKAGE
CERDIP TEMPERATURE RANGE 2MHz = 125K BAUD -55oC to +125oC HD1-6402R/883 8MHz = 500K BAUD
HD1-6402B/883 PKG. NO.
F40.6 Pinout
HD-6402/883 (CERDIP)
TOP VIEW FN2953 Rev 1.00
March 1997 VCC 1 40 TRC NC 2 39 EPE GND 3 38 CLS1 RRD 4 37 CLS2 RBR8 5 36 SBS RBR7 6 35 PI RBR6 7 34 CRL RBR5 8 33 TBR8 RBR4 9 32 TBR7 RBR3 10 31 TBR6 RBR2 11 30 TBR5 RBR1 12 29 TBR4 PE 13 28 TBR3 FE 14 27 TBR2 OE 15 26 TBR1 SFD 16 25 TRO RRC 17 24 TRE DRR 18 23 TBRL DR 19 22 TBRE RRI 20 21 MR Page 1 of 6 HD-6402/883 Control Definition
CONTROL WORD CHARACTER FORMAT CLS 2 CLS 1 PI EPE SBS START BIT DATA BITS PARITY BIT STOP BITS 0 0 0 0 0 1 5 ODD 1 0 0 0 0 1 1 5 ODD 1.5 0 0 0 1 0 1 5 EVEN 1 0 0 0 1 1 1 5 EVEN 1.5 0 0 1 X 0 1 5 NONE 1 0 0 1 X 1 1 5 NONE 1.5 0 1 0 0 0 1 6 ODD 1 0 1 0 0 1 1 6 ODD 2 0 1 0 1 0 1 6 EVEN 1 0 1 0 1 1 1 6 EVEN 2 0 1 1 X 0 1 6 NONE 1 0 1 1 x 1 1 6 NONE 2 1 0 0 0 0 1 7 ODD 1 1 0 0 0 1 1 7 ODD 2 1 0 0 1 0 1 7 EVEN 1 1 0 0 1 1 1 7 EVEN 2 1 0 1 X 0 1 7 NONE 1 1 0 1 x 1 1 7 NONE 2 1 1 0 0 0 1 8 ODD 1 1 1 0 0 1 1 8 ODD 2 1 1 0 1 0 1 8 EVEN 1 1 1 0 1 1 1 8 EVEN 2 1 1 1 X 0 1 8 NONE 1 1 1 1 x 1 1 8 NONE 2 FN2953 Rev 1.00
March 1997 Page 2 of 6 HD …