Корпус Intersil L8.3x3G — Даташит

Plastic Packages for Integrated Circuits Package Outline Drawing
L8.3x3G
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN)
Rev 1, 5/15 PIN 1 INDEX AREA 3.00
B 1.45 A PIN 1 INDEX AREA 0.075 C
4X 6X 0.50 BSC
3.00 1.50
REF 1.75 8X 0.25
0.10 M C A B 8X 0.40 2.20 TOP VIEW BOTTOM VIEW (8X 0.60) (8X 0.25) SEE DETAIL X''
0.10 C
0.75 C (1.75) SEATING PLANE
0.08 C (6X 0.50 BSC) SIDE VIEW
(1.45)
(2.20) TYPICAL RECOMMENDED LAND PATTERN c 0.20 REF 5 0~0.05 DETAIL “X” NOTES:
1. Controlling dimensions are in mm.
Dimensions in ( ) for reference only.
2. Unless otherwise specified, tolerance: Decimal В±0.05
Angular В±2В°
3. Dimensioning and tolerancing conform to JEDEC STD MO220-D.
4. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be either
a mold or mark feature.
5. Tiebar shown (if present) is a non-functional feature and may be …