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Datasheet Intersil CD40105BKMSR

ѕроизводительIntersil
—ери€CD40105BMS
ћодельCD40105BKMSR

CMOS FIFO Register

Datasheets

  • —качать » Datasheet, PDF, 327  б, ¬ерси€: 2017-12-21
    CD40105BMS Datasheet
    ¬ыписка из документа ↓
    DATASHEET
    CD40105BMS FN3353
    Rev 0.00
    December 1992 CMOS FIFO Register Features Description 4 Bits x 16 Words CD40105BMS is a low-power first-in-first-out (FIFO) вАЬelasticвАЭ
    storage register that can store 16 4-bit words. It is capable of
    handling input and output data at different shifting rates. This
    feature makes it particularly useful as a buffer between asynchronous systems. High Voltage Type (20V Rating) Independent Asynchronous Inputs and Outputs 3-State Outputs Expandable in Either Direction Status Indicators on Input and Output Reset Capability Standardized Symmetrical Output Characteristics 100% Tested for Quiescent Current at 20V 5V, 10V and 15V Parametric Ratings Maximum Input Current of 1пБ≠A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC Noise Margin (Over Full Package/Temperature Range)
    -1V at VDD = 5V
    -2V at VDD = 10V
    -2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard
    No. 13B, вАЬStandard Specifications for Description of
    вАШBвАЩ Series CMOS DevicesвАЭ Each word position in the register is clocked by a control flipflop, which stores a marker bit. A вАЬ1вАЭ signifies that the positionвАЩs data is filled and a вАЬ0вАЭ denotes a vacancy in that position. The control flip-flop detects the state of the preceding
    flip-flop and communicates its own status to the succeeding
    flip-flop. When a control flip-flop is in the вАЬ0вАЭ state and sees a
    вАЬ1вАЭ in the preceding flip-flop, it generates a clock pulse that
    transfers data from the preceding four data latches into its
    own four data latches and resets the preceding flip-flop to
    вАЬ0вАЭ. The first and last control flip-flops have buffered outputs.
    Since all empty locations вАЬbubbleвАЭ automatically to the input
    end, and all valid data ripple through to the output end, the
    status of the first control flip-flop (DATA-IN READY) indicates
    if the FIFO is full, and the status of the last flip-flop (DATAOUT READY) indicates if the FIFO contains data. As the
    earliest data are removed from the bottom of the data stack ...

÷ены

 орпус / ”паковка / ћаркировка

 орпус16 Ld CFP
»ндекс корпусаK16.A

ѕараметры

ClassV
DLA SMD5962-96602
DescriptionCMOS FIFO Register
High Dose Rate (HDR) krad(Si)100
Low Dose Rate (ELDRS) krad(Si)ELDRS free
–абочий диапазон температурот -55 до 125
Qualification LevelQML Class V (space)
SEL (MeV/mg/cm2)75

Ёкологический статус

RoHS—овместим

ћодельный р€д

—ери€: CD40105BMS (2)

 лассификаци€ производител€

  • Space & Harsh Environment > Rad Hard Digital > RH Shift Registers

Ќа английском €зыке: Datasheet Intersil CD40105BKMSR

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