Datasheet Microchip PL500-15 — Даташит

PL500-15/16
Low Phase Noise VCXO (1MHz to 18MHz)
FEATURES п‚ п‚ п‚ XIN 1 VCON 2 DIVSEL^ 3 GND 4 8 XOUT 7 OE^ 6 VDD 5 CLK SOP-8L VCON 1 GND 2 XIN 3 PL500-15/16 п‚ п‚ п‚ п‚ п‚ п‚ п‚ VCXO with Divider Selection (DIVSEL) input pin
п‚ PL500-15: Г 8, Г 16
п‚ PL500-16: Г 2, Г 4
VCXO output for the 1MHz to 18MHz range
16MHz to 36MHz fundamental crystal i nput.
Low phase noise (-130 dBc @ 10kHz offset
using a 35.328MHz crystal).
LVCMOS output with OE tri-state control.
Integrated high linearity variable capacitors.
12mA drive capability at TTL output.
В± 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5V ~ 3.3V operation.
Available in 8-Pin SOP, 6-pin SOT23 GREEN/
RoHS compliant packages, or DIE. PL500-15/16 п‚ PIN CONFIGURATION 6 CLK 5 VDD 4 XOUT SOT23-6L*
^: Denotes internal Pull-up
*: SOT package offers single divider option only DESCRIPTION
The PL500-15/16 is a low cost, high performance
and low phase noise VCXO for the 1MHz to 18MHz
range, providing less than -130dBc at 10kHz offset
when using a 35.328MHz crystal. The very low jitter …